DS92001_06 Datasheet, PDF (9/12 Pages) National Semiconductor (TI) – 3.3V B/LVDS-BLVDS Buffer

Application Information
The DS92001 can be used as a "stub-hider." In many sys-
tems, signals are distributed across backplanes, and one of
the limiting factors for system speed is the "stub length" or
the distance between the transmission line and the untermi-
nated receivers on the individual cards. See Figure 10.
Although it is generally recognized that this distance should
be as short as possible to maximize system performance,
real-world packaging concerns and PCB designs often make
it difficult to make the stubs as short as the designer would
like. The DS92001, available in the LLP (Leadless Lead-
frame Package) package, can improve system performance
by allowing the receiver to be placed very close to the main
transmission line either on the backplane itself or very close
to the connector on the card. Longer traces to the LVDS
receiver may be placed after the DS92001. This very small
LLP package is a 75% space savings over the SOIC pack-
age.
The DS92001 may also be used as a repeater as shown in
Figure 11. The signal is recovered and redriven at full
strength down the following segment. The DS92001 may
also be used as a level translator, as it accepts LVDS,
BLVDS, and LVPECL inputs.
LOS DETECTION
The LOS pin presents a logic High level during normal
operation (|100|mV ≤ V_ID ≤ |2|V, of the device. When normal
transmission stops the LOS pin is asserted low. This occurs
when the signal’s source is removed, or turned-off (TRI-
STATE). When the input signal voltage (V_ID) is less than |10|
millivolts the LOS pin is asserted Low. For normal operation,
Rise and Fall times presented to the B/LVDS inputs must be
faster than 20 nanoseconds (20% to 80%) to avoid a loss of
signal detection. Typical input transitions are in the 1-3 nano-
second range. In the case of a decaying signal (such as valid
signal to TRI-STATE), the slope should be monotonic to
avoid glitches in the LOS detection.
LOS Detection - Output Low
POWER DECOUPLING RECOMMENDATIONS
Bypass capacitors must be used on power pins. Use high
frequency ceramic (surface mount is recommended) 0.1µF
and 0.01µF capacitors in parallel at the power supply pin
with the smallest value capacitor closest to the device supply
pin. Additional scattered capacitors over the printed circuit
board will improve decoupling. Multiple vias should be used
to connect the decoupling capacitors to the power planes. A
10µF (35V) or greater solid tantalum capacitor should be
connected at the power entry point on the printed circuit
board between the supply and ground.
PC BOARD CONSIDERATIONS
Use at least 4 PCB board layers (top to bottom): LVDS
signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
signals may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a
power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
For PC board considerations for the LLP package, please
refer to application note AN-1187 “Leadless Leadframe
Package.” It is important to note that to optimize signal
integrity (minimize jitter and noise coupling), the LLP thermal
land pad, which is a metal (normally copper) rectangular
region located under the package as seen in Figure 12,
should be attached to ground and match the dimensions of
the exposed pad on the PCB (1:1 ratio).
20024744
FIGURE 12. LLP Thermal Land Pad and Pin Pads - Top View
DIFFERENTIAL TRACES
Use controlled impedance traces which match the differen-
tial impedance of your transmission medium (ie. cable) and
termination resistor. Run the differential pair trace lines as
close together as possible as soon as they leave the IC
(stubs should be < 10mm long). This will help eliminate
reflections and ensure noise is coupled as common-mode.
In fact, we have seen that differential signals which are 1mm
apart radiate far less noise than traces 3mm apart since
magnetic field cancellation is much better with the closer
traces. In addition, noise induced on the differential lines is
much more likely to appear as common-mode which is re-
jected by the receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase differ-
ence between signals which destroys the magnetic field
cancellation benefits of differential signals and EMI will re-
sult. Do not rely solely on the auto-route function for differ-
ential traces. Carefully review dimensions to match differen-
tial impedance and provide isolation for the differential lines.
Minimize the number of vias and other discontinuities on the
line.
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