DS92001_06 Datasheet, PDF (7/12 Pages) National Semiconductor (TI) – 3.3V B/LVDS-BLVDS Buffer

AC Test Circuits and Timing Diagrams (Continued)
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FIGURE 9. LOS Output Waveforms for Propagation Delay, and Rise/Fall Times
DS92001 Pin Descriptions (SOIC and LLP)
Pin Name
GND
IN −
IN+
LOS
V_CC
OUT+
OUT -
EN
GND
Pin #
1
2
3
4
5
6
7
8
DAP
Input/Output
P
I
I
O
P
O
O
I
P
Description
Ground
Inverting receiver B/LVDS input pin
Non-inverting receiver B/LVDS input pin
Loss of Signal output pin. LOS is asserted low while signal is invalid.
See Applications Information section.
Power Supply, 3.3V ± 0.3V.
Non-inverting driver BLVDS output pin
Inverting driver BLVDS output pin
Enable pin. When EN is LOW, the driver is disabled and the BLVDS
outputs are in TRI-STATE. When EN is HIGH, the driver is enabled.
LVCMOS/LVTTL levels.
LLP Package Ground
7
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