DS92001_06 Datasheet, PDF (6/12 Pages) National Semiconductor (TI) – 3.3V B/LVDS-BLVDS Buffer

AC Test Circuits and Timing Diagrams (Continued)
FIGURE 5. BLVDS Output Transition Time
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FIGURE 6. TRI-STATE Delay Test Circuit
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FIGURE 7. Output active to TRI-STATE and TRI-STATE to active output time
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FIGURE 8. LOS Output Load for Propagation Delay, and Rise/Fall Times
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