DS90C365A_05 Datasheet, PDF (9/12 Pages) National Semiconductor (TI) – +3.3V programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz

AC Timing Diagrams (Continued)
FIGURE 12. Transmitter LVDS Output Pulse Position Measurement - DS90C365A
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DS90C365A MTD48 (TSSOP) Package Pin Descriptions — FPD Link
Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
TxCLKIN
R_FB
TxCLK OUT+
TxCLK OUT−
PWR DOWN
V_CC
GND
PLL V_CC
PLL GND
LVDS V_CC
LVDS GND
NC
I/O No.
Description
I
21 LVTTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
O
3 Positive LVDS differentiaI data output.
O
3 Negative LVDS differential data output.
I
1 LVTTL Ievel clock input. Pin name TxCLK IN.
I
1 LVTTL Ievel programmable strobe select (See Table 1).
O
1 Positive LVDS differential clock output.
O
1 Negative LVDS differential clock output.
I
1 LVTTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current
at power down.
I
3 Power supply pins for LVTTL inputs.
I
5 Ground pins for LVTTL inputs.
I
1 Power supply pin for PLL.
I
2 Ground pins for PLL.
I
1 Power supply pin for LVDS outputs.
I
3 Ground pins for LVDS outputs.
1 No connect
9
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