DS90C365A_05 Datasheet, PDF (5/12 Pages) National Semiconductor (TI) – +3.3V programmable LVDS Transmitter 18-Bit Flat Panel Display Link-87.5 MHz

Transmitter Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
TCCD
TxCLK IN to TxCLK OUT Delay. Measure from
TxCLK IN edge to immediatley crossing poing
of differential TxCLK OUT by following the
postive TxCLK OUT. 50% duty cycle input clock
is assumed. (Figure 7)
T_A = −10˚C,
and 85MHz
for ” Min ”
T_A = 70˚C,
and 25MHz
for ” Max ”,
V_CC = 3.6V,
R_FB pin =
VCC
3.086
Measure from TxCLK IN edge to immediatley
crossing poing of differential TxCLK OUT by
following the postive TxCLK OUT. 50% duty
cycle input clock is assumed. (Figure 8)
T_A = −10˚C,
and 85MHz
for ” Min ”
T_A = 70˚C,
and 25MHz
for ” Max ”,
V_CC = 3.6V,
R_FB pin =
GND
2.868
SSCG
Spread Spectrum Clock support; Modulation
frequency with a linear profile.(Note 6)
f = 25 MHz
f = 40 MHz
f = 65 MHz
TPLLS
TPDD
Transmitter Phase Lock Loop Set (Figure 9)
Transmitter Power Down Delay (Figure 11)
f = 87.5
MHz
Typ
100kHz ±
2.5%/−5%
100kHz ±
2.5%/−5%
100kHz ±
2.5%/−5%
100kHz ±
2.5%/−5%
Max
7.211
6.062
10
100
Units
ns
ns
ms
ns
Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This
parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 6: Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the performance of tracking
Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLKOUT− pins.
5
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