DP83847 Datasheet, PDF (9/60 Pages) National Semiconductor (TI) – DsPHYTER II ㅡ Single 10/100 Ethernet Transceiver

Signal Name
RX_ER/PAUSE_EN
CRS/LED_CFG
1.7 Reset
Type
S, O, PU
S, O_,
PU
LLP Pin #
Description
33 PAUSE ENABLE: This strapping option allows advertisement of
whether or not the DTE(MAC) has implemented both the optional
MAC control sublayer and the pause function as specified in
clause 31 and annex 31B of the IEEE 802.3x specification (Full
Duplex Flow Control).
When left floating the Auto-Negotiation Advertisement Register
will be set to 0, indicating that Full Duplex Flow Control is not sup-
ported.
When tied low through a 5 kΩ, the Auto-Negotiation Advertise-
ment Register will be set to 1, indicating that Full Duplex Flow
Control is supported.
The float/pull-down status of this pin is latched into the Auto-Ne-
gotiation Advertisement Register during Hardware-Reset.
45 LED CONFIGURATION: This strapping option defines the polar-
ity and function of the FDPLX LED pin.
See Section 2.3 for further descriptions of this strapping option.
Signal Name
RESET
Type
I
1.8 Power and Ground Pin
LLP Pin #
Description
46 RESET: Active Low input that initializes or re-initializes the
DP83847. Asserting this pin low for at least 160 µs will force a re-
set process to occur which will result in all internal registers re-ini-
tializing to their default states as specified for each bit in the
Register Block section and all strapping options are re-initialized.
Signal Name
LLP Pin #
TTL/CMOS INPUT/OUTPUT SUPPLY
IO_VDD
28, 56
IO_GND
GND
INTERNAL SUPPLY PAIRS
CORE_VDD
Internal
CORE_GND
GND
ANALOG SUPPLY PINS
ANA_VDD
14
ANA_GND
GND
SUBSTRATE GROUND
SUB_GND
GND
Description
I/O Supply
I/O Ground
Digital Core Supply
Digital Core Ground
Analog Supply
Analog Ground
Bandgap Substrate connection
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