DP83847 Datasheet, PDF (15/60 Pages) National Semiconductor (TI) – DsPHYTER II ㅡ Single 10/100 Ethernet Transceiver

3.0 Functional Description
3.1 802.3u MII
The DP83847 incorporates the Media Independent Inter-
face (MII) as specified in Clause 22 of the IEEE 802.3u
standard. This interface may be used to connect PHY
devices to a MAC in 10/100 Mb/s systems. This section
describes both the serial MII management interface as well
as the nibble wide MII data interface.
The serial management interface of the MII allows for the
configuration and control of multiple PHY devices, gather-
ing of status, error information, and the determination of the
type and capabilities of the attached PHY(s).
The nibble wide MII data interface consists of a receive bus
and a transmit bus each with control signals to facilitate
data transfer between the PHY and the upper layer (MAC).
3.1.1 Serial Management Register Access
The serial management MII specification defines a set of
thirty-two 16-bit status and control registers that are acces-
sible through the management interface pins MDC and
MDIO. The DP83847 implements all the required MII regis-
ters as well as several optional registers. These registers
are fully described in Section 4.0. A description of the serial
management access protocol follows.
3.1.2 Serial Management Access Protocol
The serial control interface consists of two pins, Manage-
ment Data Clock (MDC) and Management Data Input/Out-
put (MDIO). MDC has a maximum clock rate of 25 MHz
and no minimum rate. The MDIO line is bi-directional and
may be shared by up to 32 devices. The MDIO frame for-
mat is shown below in Table 4: Typical MDIO Frame For-
mat.
The MDIO pin requires a pull-up resistor (1.5 kΩ) which,
during IDLE and turnaround, will pull MDIO high. In order to
initialize the MDIO interface, the station management entity
sends a sequence of 32 contiguous logic ones on MDIO to
provide the DP83847 with a sequence that can be used to
establish synchronization. This preamble may be gener-
ated either by driving MDIO high for 32 consecutive MDC
clock cycles, or by simply allowing the MDIO pull-up resis-
tor to pull the MDIO pin high during which time 32 MDC
clock cycles are provided. In addition 32 MDC clock cycles
should be used to re-sync the device if an invalid start,
opcode, or turnaround bit is detected.
The DP83847 waits until it has received this preamble
sequence before responding to any other transaction.
Once the DP83847 serial management port has been ini-
tialized no further preamble sequencing is required until
after a power-on/reset, invalid Start, invalid Opcode, or
invalid turnaround bit has occurred.
The Start code is indicated by a <01> pattern. This assures
the MDIO line transitions from the default idle line state.
Turnaround is defined as an idle bit time inserted between
the Register Address field and the Data field. To avoid con-
tention during a read transaction, no device shall actively
drive the MDIO signal during the first bit of Turnaround.
The addressed DP83847 drives the MDIO with a zero for
the second bit of turnaround and follows this with the
required data. Figure 2 shows the timing relationship
between MDC and the MDIO as driven/received by the Sta-
tion (STA) and the DP83847 (PHY) for a typical register
read access.
MII Management
Serial Protocol
Read Operation
Write Operation
Table 4. Typical MDIO Frame Format
<idle><start><op code><device addr><reg addr><turnaround><data><idle>
<idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>
<idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>
MDC
MDIO ^Z
Z
(STA)
MDIO
Z
Z
(PHY)
Z _{01 1 0 0 1 1 0 0 0 0 0 0 0}Z_{0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0} Z
Idle
Start
Opcode
(Read)
PHY Address
(PHYAD = 0Ch)
Register Address
(00h = BMCR)
TA
Register Data
Idle
Figure 2. Typical MDC/MDIO Read Operation
For write transactions, the station management entity
writes data to the addressed DP83847 thus eliminating the
requirement for MDIO Turnaround. The Turnaround time is
filled by the management entity by inserting <10>. Figure 3
shows the timing relationship for a typical MII register write
access.
3.1.3 Serial Management Preamble Suppression
The DP83847 supports a Preamble Suppression mode as
indicated by a one in bit 6 of the Basic Mode Status Regis-
ter (BMSR, address 01h.) If the station management entity
(i.e. MAC or other management controller) determines that
all PHYs in the system support Preamble Suppression by
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