DP83932C-20 Datasheet, PDF (85/98 Pages) National Semiconductor (TI) – MHz SONICTM Systems-Oriented Network Interface Controller

7 0 AC and DC Specifications (Continued)
BUS REQUEST TIMING BMODE e 1
TL F 10492 – 68
Number
Parameter
20 MHz
Min Max
25 MHz
Min Max
33 MHz
Min Max
Units
T45a
BG AS BGACK DSACK0 1 and STERM
7
6
5
ns
Asynchronous Setup Time to BSCK (Note 1)
T51a
BSCK to Address AS MRW DS ECS
USR^k1 0^l and EXUSR^k3 0^l TRI-STATE
34
32
30
ns
T52
BSCK to Data TRI-STATE
34
32
30
ns
T53
BSCK to Address AS MRW DS ECS
34
32
30
ns
USR^k1 0^l and EXUSR^k3 0^l Active (Note 1)
T54
BSCK Low to BR Low TRI-STATE
23
21
19
ns
T54a
BSCK High to BGACK Low High
24
22
20
ns
T54b
BSCK High to BGACK TRI-STATE
19
17
15
ns
T55
BSCK to Bus Status Valid
29
27
25
ns
T55b
S^k2 0^l Hold from BSCK
3
3
3
ns
Note 1 BGACK is asserted one bus clock after all the signals (AS DSACK0 1 BGACK STERM (Extended bus mode) and BG) meet the T45a setup time (see
Section 5 4 1 for more information) The address bus AS DS ECS MRW USRk1 0l and EXUSRk3 0l will also be driven active on the same clock
Note 2 Sk2 0l will indicate IDLE at the end of T2 if the last operation is a read operation or at the end of Th if the last operation is a write operation
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