DP83932C-20 Datasheet, PDF (60/98 Pages) National Semiconductor (TI) – MHz SONICTM Systems-Oriented Network Interface Controller

5 0 Bus Interface (Continued)
5 4 5 4 Memory Cycle for BMODE e 0 Synchronous
Mode
On the rising edge of T1 the SONIC asserts ADS and ECS
to indicate that the memory cycle is starting The address
(A31-A1) bus status (S2-S0) and the direction strobe
(MWR) are driven and do not change for the remainder of
the memory cycle On the falling edge of T1 the SONIC
deasserts ECS ADS is deasserted on the rising edge of T2
In Synchronous mode RDYi is sampled on the rising edge
at the end of T2 (the rising edge of the next T1) T2 states
will be repeated until RDYi is sampled properly in a low
state RDYi must meet the setup and hold times with re-
spect to the rising edge of bus clock for proper operation
During read cycles (Figure 5-14 ) data (D31-D0) is latched
at the rising edge at the end of T2 For write cycles (Figure
5-15 ) data is driven on the rising edge of T1 and stays driv-
en until the end of the cycle
FIGURE 5-14 Memory Read BMODEe0 Synchronous (1 Wait-State)
TL F 10492 – 38
FIGURE 5-15 Memory Write BMODEe0 Synchronous (1 Wait-State)
60
TL F 10492 – 40