LP3950 Datasheet, PDF (8/31 Pages) National Semiconductor (TI) – Color LED Driver with Audio Synchronizer

Logic Interface Characteristics (Continued)
(1.80V ≤ V_DDIO ≤ V_DD1,2V). Limits in standard typeface are for T_J = +25˚C. Limits in boldface type apply over the operating
ambient temperature range (−40˚C ≤ T_A ≤ +85˚C).
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LOGIC INPUTS DME, AMODE (Internal pull down 1 MΩ)
I_I
Logic Input Current
−1.0
6.0
µA
Logic Interface Characteristics, Low I/O Voltage
(1.65V ≤ V_DDIO < 1.80V) . I²C compatible interface only.
Symbol
Parameter
Conditions
Min
Typ
LOGIC INPUTS SCL, PWM_LED, IF_SEL
V_IL
Input Low Level
V_IH
Input High Level
I_I
Logic Input Current
f_SCL
Clock Frequency
LOGIC I/O SDA
I²C Mode
V_DDIO − 0.35
−1.0
V_OL
Output Low Level
I_SDA = 3.0 mA
0.3
LOGIC INPUTS DME, AMODE (Internal pull down 1 MΩ)
V_IL
Input Low Level
V_IH
Input High Level
I_I
Logic Input Current
V_DDIO − 0.35
−1.0
Max
Units
0.35
V
V
1.0
µA
200
kHz
0.5
V
0.35
V
V
6.0
µA
Logic Input NRST Characteristics
(1.65V ≤ V_DDIO ≤ V_DD1,2V).
Symbol
Parameter
Conditions
V_IL
V_IH
I_I
t_NRST
Input Low Level
Input High Level
Logic Input Current
Reset Pulse Width
Note: Guaranteed by
design
Control Interface
The LP3950 supports three different interface modes:
1) SPI interface (4 wire, serial)
2) I²C compatible interface (2 wire, serial)
3) Direct enable (2 wire, enable lines)
IF_SEL
Interface
HIGH SPI
LOW I²C Compatible
Pin Configuration
SCK
(clock)
SI
(data in)
SO
(data out)
SS
(chip select)
SCL
(clock)
SDA
SI
(data in/out)
(I² address)
SO
(NC)
SPI Interface
The transmission consists of 16-bit write and read cycles.
One cycle consists of seven address bits, one read/write
(R/W) bit and eight data bits. R/W bit high state defines a
write cycle and low defines a read cycle. SO output is
normally in high-impedance state and it is active only during
Min
1.3
−1.0
10
Typ
Max
Units
0.5
V
V
1.0
µA
µs
User can define the serial interface by the IF_SEL pin. The
following table shows the pin configuration for both interface
modes. Note that the pin configurations will be based on the
status of the IF_SEL pin.
Comment
Use pull up resistor for SCL.
Use pull up resistor for SDA.
SI HIGH → address is 51’h;
SI LOW → address is 50’h;
Unused pin SO can be left unconnected.
when data is sent out during a read cycle. A pull-up or
pull-down resistor may be needed for SO line if a floating
logic signal can cause unintended current consumption in
the circuitry.
The address and data are transmitted Most Significant Byte
(MSB) first. The Slave Select signal (SS) must be low during
the cycle transmission. SS resets the interface when high
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