LP3950 Datasheet, PDF (6/31 Pages) National Semiconductor (TI) – Color LED Driver with Audio Synchronizer

Block Diagram
FIGURE 1. LP3950 Block Diagram
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Modes of Operation
RESET:
In the RESET mode all the internal registers are reset to the default values. RESET is entered always if
input NRST is LOW or internal Power On Reset is active.
STANDBY:
The STANDBY mode is entered if the register bit NSTBY is LOW and RESET is not active. This is the low
power consumption mode, when all the circuit functions are disabled. Registers can be written in this mode
and the control bits are effective immediately after start up.
STARTUP:
INTERNAL STARTUP SEQUENCE powers up all the needed internal blocks (V_REF, oscillator, etc.). To
ensure the correct oscillator initialization, a 10 ms delay is generated by the internal state-machine. Thermal
shutdown (THSD) disables the chip operation and Startup mode is entered until no thermal shutdown event
is present.
BOOST STARTUP: Soft start for boost output is generated in the BOOST STARTUP mode. In this mode the boost output is
raised in PFM mode during the 10 ms delay generated by the state-machine. All RGB outputs are off during
the 10 ms delay to ensure smooth startup. The Boost startup is entered from Internal Startup Sequence if
EN_BOOST is HIGH or from Normal mode when EN_BOOST is written HIGH.
NORMAL:
During the NORMAL mode the user controls the chip using the control registers. Registers can be written
in any sequence and any number of bits can be altered in a register within one write cycle . If the default
mode is selected, default control register values are used.
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