LP3950 Datasheet, PDF (11/31 Pages) National Semiconductor (TI) – Color LED Driver with Audio Synchronizer

I²C Compatible Interface (Continued)
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FIGURE 6. Start and Stop Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse. The receiver must pull down the
SDA line during the 9th clock pulse, signifying an acknowl-
edge. A receiver which has been addressed must generate
an acknowledge after each byte has been received.
After the START condition, the I²C master sends a chip
address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LP3950
address is 50’h or 51’h. The selection of the address is done
by connecting SI pin to V_DDIO (51 hex) or GND (50 hex). For
the eighth bit, a “0” indicates a WRITE and a “1” indicates a
READ. The second byte selects the register to which the
data will be written. The third byte contains data to write to
the selected register.
FIGURE 7. I²C Chip Address
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w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = chip address, 50’h or 51’h for LP3950.
FIGURE 8. I²C Write Cycle
When a READ function is to be accomplished, a WRITE
function must precede the READ function, as shown in
Figure 9 .
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