DS90CR281 Datasheet, PDF (8/14 Pages) National Semiconductor (TI) – 28-Bit Channel Link

AC Timing Diagrams (Continued)
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FIGURE 11. DS90CR282 (Receiver) Phase Lock Loop Set Time
FIGURE 12. Seven Bits of LVDS in One Clock Cycle
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FIGURE 13. 28 Parallel TTL Data Inputs Mapped to LVDS Outputs (DS90CR281)
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FIGURE 14. Transmitter Powerdown Delay
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