DS90CR281 Datasheet, PDF (1/14 Pages) National Semiconductor (TI) – 28-Bit Channel Link

July 1997
DS90CR281/DS90CR282
28-Bit Channel Link
General Description
The DS90CR281 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. The DS90CR282 receiver converts the LVDS
data streams back into 28 bits of CMOS/TTL data. At a trans-
mit clock frequency of 40 MHz, 28 bits of TTL data are trans-
mitted at a rate of 280 Mbps per LVDS data channel. Using
a 40 MHz clock, the data throughput is 1.12 Gbit/s
(140 Mbytes/s).
The multiplexing of the data lines provides a substantial
cable reduction. Long distance parallel single-ended buses
typically require a ground wire per active signal (and have
very limited noise rejection capability). Thus, for a 28-bit wide
data bus and one clock, up to 58 conductors are required.
With the Channel Link chipset as few as 11 conductors (4
data pairs, 1 clock pair and a minimum of one
ground) are needed. This provides a 80% reduction in re-
quired cable width, which provides a system cost savings,
reduces connector physical size and cost, and reduces
shielding requirements due to the cables’ smaller form fac-
tor.
The 28 CMOS/TTL inputs can support a variety of signal
combinations. For example, 7 4-bit nibbles or 3 9-bit (byte +
parity) and 1 control.
Features
n Narrow bus reduces cable size and cost
n ±1V common mode range (ground shifting)
n 290 mV swing LVDS data transmission
n 1.12 Gbit/s data throughput
n Low swing differential current mode drivers reduce EMI
n Rising edge data strobe
n Power down mode
n Offered in low profile 56-lead TSSOP package
Block Diagrams
DS90CR281
DS90CR282
DS012638-27
Order Number DS90CR281MTD
See NS Package Number MTD56
DS012638-1
Order Number DS90CR282MTD
See NS Package Number MTD56
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