DS15MB200_0605 Datasheet, PDF (8/10 Pages) National Semiconductor (TI) – Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis

TRI-STATE and Powerdown Modes
The DS15MB200 has output enable control on each of the
six onboard LVDS output drivers. This control allows each
output individually to be placed in a low power TRI-STATE
mode while the device remains active, and is useful to
reduce power consumption on unused channels. In TRI-
STATE mode, some outputs may remain active while some
are in TRI-STATE.
When all six of the output enables (all drivers on both chan-
nels) are deasserted (LOW), then the device enters a Pow-
erdown mode that consumes only 0.5mA (typical) of supply
current. In this mode, the entire device is essentially pow-
ered off, including all receiver inputs, output drivers and
internal bandgap reference generators. When returning to
active mode from Powerdown mode, there is a delay until
valid data is presented at the outputs because of the ramp to
power up the internal bandgap reference generators.
Any single output enable that remains active will hold the
device in active mode even if the other five outputs are in
TRI-STATE.
When in Powerdown mode, any output enable that becomes
active will wake up the device back into active mode, even if
the other five outputs are in TRI-STATE.
Input Failsafe Biasing
External pull up and pull down resistors may be used to
provide enough of an offset to enable an input failsafe under
open-circuit conditions. This configuration ties the positive
LVDS input pin to VDD thru a pull up resistor and the
negative LVDS input pin is tied to GND by a pull down
resistor. The pull up and pull down resistors should be in the
5kΩ to 15kΩ range to minimize loading and waveform dis-
tortion to the driver. The common-mode bias point ideally
should be set to approximately 1.2V (less than 1.75V) to be
compatible with the internal circuitry. Please refer to applica-
tion note AN-1194, “Failsafe Biasing of LVDS Interfaces” for
more information.
Interfacing LVPECL to LVDS
An LVPECL driver consists of a differential pair with coupled
emitters connected to GND via a current source. This drives
a pair of emitter-followers that require a 50 ohm to V_CC-2.0
load. A modern LVPECL driver will typically include the ter-
mination scheme within the device for the emitter follower. If
the driver does not include the load, then an external
scheme must be used. The 1.3 V supply is usually not
readily available on a PCB, therefore, a load scheme without
a unique power supply requirement may be used.
driver device (Note 16). The 15MB200 includes a 100 ohm
input termination for the transmission line. The common
mode voltage will be at the normal LVPECL levels – around
2 V. This scheme works well with LVDS receivers that have
rail-to-rail common mode voltage, V_CM, range. Most National
Semiconductor LVDS receivers have wide V_CM range. The
exceptions are noted in devices’ respective datasheets.
Those LVDS devices that do have a wide V_CM range do not
vary in performance significantly when receiving a signal
with a common mode other than standard LVDS V_CM of 1.2
V.
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FIGURE 3. AC Coupled LVPECL to LVDS Interface
An AC coupled interface is preferred when transmitter and
receiver ground references differ more than 1 V. This is a
likely scenario when transmitter and receiver devices are on
separate PCBs. Figure 3 illustrates an AC coupled interface
between a LVPECL driver and LVDS receiver. R1 and R2, if
not present in the driver device (Note 16), provide DC load
for the emitter followers and may range between 140-220
ohms for most LVPECL devices for this particular configura-
tion. The 15MB200 includes an internal 100 ohm resistor to
terminate the transmission line for minimal reflections. The
signal after ac coupling capacitors will swing around a level
set by internal biasing resistors (i.e. fail-safe) which is either
V_DD/2 or 0 V depending on the actual failsafe implementa-
tion. If internal biasing is not implemented, the signal com-
mon mode voltage will slowly wander to GND level.
20157361
FIGURE 2. DC Coupled LVPECL to LVDS Interface
Figure 2 is a separated π termination scheme for a 3.3 V
LVPECL driver. R1 and R2 provides proper DC load for the
driver emitter followers, and may be included as part of the
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