DS15MB200_0605 Datasheet, PDF (6/10 Pages) National Semiconductor (TI) – Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Typ
Min
Max
(Note 8)
Units
SUPPLY CURRENT (Static)
I_CC
Supply Current
All inputs and outputs enabled and
active, terminated with external load of
100Ω between OUT+ and OUT-.
225
275
mA
I_CCZ
Supply Current - Powerdown
ENA_0 = ENB_0 = ENL_0 = ENA_1 =
Mode
ENB_1 = ENL_1 = L
0.6
4.0
SWITCHING CHARACTERISTICS — LVDS OUTPUTS
t_LHT
Differential Low to High Transition Use an alternating 1 and 0 pattern at
Time
200 Mb/s, measure between 20% and
t_HLT
Differential High to Low Transition ^{80% of V}OD^{. (Note 15)}
Time
170
250
ps
170
250
ps
t_PLHD
t_PHLD
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Use an alternating 1 and 0 pattern at
200 Mb/s, measure at 50% V_OD
between input to output.
1.0
2.5
ns
1.0
2.5
ns
t_SKD1
t_SKCC
Pulse Skew
Output Channel to Channel Skew
|t_PLHD–t_PHLD| (Note 15)
Difference in propagation delay (t_PLHD
or t_PHLD) among all output channels.
(Note 15)
25
75
ps
50
115
ps
t_JIT
Jitter (0% Pre-emphasis)
(Note 11)
RJ - Alternating 1 and 0 at 750MHz
(Note 12)
1.1
1.5
psrms
DJ - K28.5 Pattern, 1.5 Gbps (Note 13)
TJ - PRBS 2⁷-1 Pattern, 1.5 Gbps (Note
14)
20
34
psp-p
14
28
psp-p
t_ON
LVDS Output Enable Time
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from TRI-STATE to
active.
0.5
1.5
µs
t_ON2
LVDS Output Enable Time from Time from ENA_n, ENB_n, or ENL_n to
Powerdown Mode
OUT± change from Powerdown Mode
to active.
10
20
µs
t_OFF
LVDS Output Disable Time
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from active to
TRI-STATE or Powerdown mode.
12
ns
Note 8: Typical parameters are measured at V_DD = 3.3V, T_A = 25˚C. They are for reference purposes, and are not production-tested.
Note 9: Differential output voltage V_OD is defined as ABS(OUT+–OUT−). Differential input voltage V_ID is defined as ABS(IN+–IN−).
Note 10: Output offset voltage V_OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
Note 11: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 12: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V_ID = 500mV, 50% duty cycle at
750MHz, t_r = t_f = 50ps (20% to 80%).
Note 13: Deterministic Jitter, or D_J, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter have been subtracted. The input
voltage = V_ID = 500mV, K28.5 pattern at 1.5 Gbps, t_r = t_f = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
Note 14: Total Jitter, or T_J, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter have been subtracted. The input voltage
= V_ID = 500mV, 2^7-1 PRBS pattern at 1.5 Gbps, t_r = t_f = 50ps (20% to 80%).
Note 15: Not production tested. Guaranteed by statistical analysis on a sample basis at the time of characterization.
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