DS15MB200_0605 Datasheet, PDF (2/10 Pages) National Semiconductor (TI) – Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis

Pin Descriptions
Pin
Name
LLP Pin
I/O, Type
Number
Description
SWITCH SIDE DIFFERENTIAL INPUTS
SIA_0+
SIA_0−
30
I, LVDS Switch A-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS,
29
CML, or LVPECL compatible.
SIA_1+
SIA_1−
19
I, LVDS Switch A-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS,
20
CML, or LVPECL compatible.
SIB_0+
SIB_0−
28
I, LVDS Switch B-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS,
27
CML, or LVPECL compatible.
SIB_1+
SIB_1−
21
I, LVDS Switch B-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS,
22
CML, or LVPECL compatible.
LINE SIDE DIFFERENTIAL INPUTS
LI_0+
40
I, LVDS Line-side Channel 0 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LI_0−
39
LVPECL compatible.
LI_1+
9
I, LVDS Line-side Channel 1 inverting and non-inverting differential inputs. LVDS, Bus LVDS, CML, or
LI_1−
10
LVPECL compatible.
SWITCH SIDE DIFFERENTIAL OUTPUTS
SOA_0+
34
O, LVDS Switch A-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible
SOA_0−
33
(Notes 1, 3).
SOA_1+
15
O, LVDS Switch A-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible
SOA_1−
16
(Notes 1, 3).
SOB_0+
32
O, LVDS Switch B-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible
SOB_0−
31
(Notes 1, 3).
SOB_1+
17
O, LVDS Switch B-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible
SOB_1−
18
(Notes 1, 3).
LINE SIDE DIFFERENTIAL OUTPUTS
LO_0+
LO_0−
42
O, LVDS Line-side Channel 0 inverting and non-inverting differential outputs. LVDS compatible (Notes
41
1, 3).
LO_1+
LO_1−
7
O, LVDS Line-side Channel 1 inverting and non-inverting differential outputs. LVDS compatible (Notes
8
1, 3).
DIGITAL CONTROL INTERFACE
MUX_S0
38
I, LVTTL Mux Select Control Inputs (per channel) to select which Switch-side input, A or B, is passed
MUX_S1
11
through to the Line-side.
PREA_0
26
I, LVTTL Output pre-emphasis control for Switch-side outputs. Each output driver on the Switch A-side
PREA_1
23
PREB_0
25
and B-side has a separate pin to control the pre-emphasis on or off.
PREB_1
24
PREL_0
44
I, LVTTL Output pre-emphasis control for Line-side outputs. Each output driver on the Line A-side and
PREL_1
5
B-side has a separate pin to control the pre-emphasis on or off.
ENA_0
36
I, LVTTL Output Enable Control for Switch A-side and B-side outputs. Each output driver on the A-side
ENA_1
13
and B-side has a separate enable pin.
ENB_0
35
ENB_1
14
ENL_0
ENL_1
45
I, LVTTL Output Enable Control for The Line-side outputs. Each output driver on the Line-side has a
4
separate enable pin.
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