COP888EK Datasheet, PDF (8/46 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 8k Memory, Comparator, and Single-slope A/D Capability

DC Electrical Characteristics 88xEK: (Continued)
−40˚C ≤ T_A ≤ +85˚C unless otherwise specified
Parameter
Load Capacitance on D2
Conditions
Min
Typ
Max
Units
1000
pF
AC Electrical Characteristics 88xEK:
−40˚C ≤ T_A ≤ +85˚C unless otherwise specified
Parameter
Conditions
Min
Typ
Max
Units
Instruction Cycle Time (t_c)
Crystal, Resonator,
R/C Oscillator
Inputs
4.0V ≤ V_CC ≤ 6.0V
1.0
2.5V ≤ V_CC < 4.0V
2.5
4.0V ≤ V_CC ≤ 6.0V
3.0
2.5V ≤ V_CC ≤ 4.0V
7.5
DC
µs
DC
µs
DC
µs
DC
µs
t_SETUP
4.0V ≤ V_CC ≤ 6.0V
200
2.5V ≤ V_CC < 4.0V
500
t_HOLD
4.0V ≤ V_CC ≤ 6.0V
60
2.5V ≤ V_CC < 4.0V
150
Output Propagation Delay (Note 15)
R_L = 2.2k, C_L = 100 pF
t_PD1, t_PD0
SO, SK
4.0V ≤ V_CC ≤ 6.0V
2.5V ≤ V_CC < 4.0V
All Others
4.0V ≤ V_CC ≤ 6.0V
2.5V ≤ V_CC < 4.0V
MICROWIRE Setup Time (t_UWS) (Note 15)
20
MICROWIRE Hold Time (t_UWH) (Note 15)
56
MICROWIRE Output Propagation Delay (t_UPD)
Input Pulse Width (Note 16)
ns
ns
ns
ns
0.7
µs
1.75
µs
1.0
µs
2.5
µs
ns
ns
220
ns
Interrupt Input High Time
Interrupt Input Low Time
Timer 1, 2, 3 Input High Time
Timer 1, 2, 3 Input Low Time
Reset Pulse Width
1.0
t_c
1.0
t_c
1.0
t_c
1.0
t_c
1.0
µs
Note 10: t_c = Instruction Cycle Time
Note 11: Maximum rate of voltage change must be < 0.5 V/ms.
Note 12: Supply and IDLE currents are measured with CKI driven with a square wave Oscillator, CKO driven 180˚ out of phase with CKI, inputs connected to V_CC
and outputs driven low but not connected to a load.
Note 13: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Measurement of I_DD HALT is done with device neither sourcing nor
sinking current; with L, C, G0, and G2–G5 programmed as low outputs and not driving a load; all outputs programmed low and not driving a load; all inputs tied to
V_CC; clock monitor and comparator disabled. Parameter refers to HALT mode entered via setting bit 7 of the G Port data register. Part will pull up CKI during HALT
in crystal clock mode.
Note 14: Pins G6 and RESET are designed with a high voltage input network. These pins allow input voltages > V_CC and the pins will have sink current to V_CC when
biased at voltages > V_CC(the pins do not have source current when biased at a voltage below V_CC). The effective resistance to V_CC is 750Ω (typical). These two
pins will not latch up. The voltage at the pins must be limited to < 14V. WARNING: Voltages in excess of 14V will cause damage to the pins. This warning ex-
cludes ESD transients.
Note 15: The output propagation delay is referenced to the end of the instruction cycle where the output change occurs.
Note 16: Parameter characterized but not tested.
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