COP888EK Datasheet, PDF (34/46 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 8k Memory, Comparator, and Single-slope A/D Capability

Memory Map
All RAM, ports and registers (except A and PC) are
mapped into data memory address space.
Address
Contents
S/ADD REG
0000 to 006F On-Chip RAM bytes (112 bytes)
0070 to 007F Unused RAM Address Space (Reads
As All Ones)
xx80 to xxAF Unused RAM Address Space (Reads
Undefined Data)
xxB0
Timer T3 Lower Byte
xxB1
Timer T3 Upper Byte
xxB2
Timer T3 Autoload Register T3RA
Lower Byte
xxB3
Timer T3 Autoload Register T3RA
Upper Byte
xxB4
Timer T3 Autoload Register T3RB
Lower Byte
xxB5
Timer T3 Autoload Register T3RB
Upper Byte
xxB6
Timer T3 Control Register
xxB7
Comparator Select Register (CMPSL)
xxB8 to xxBF Reserved
xxC0
Timer T2 Lower Byte
xxC1
Timer T2 Upper Byte
xxC2
Timer T2 Autoload Register T2RA
Lower Byte
xxC3
Timer T2 Autoload Register T2RA
Upper Byte
xxC4
Timer T2 Autoload Register T2RB
Lower Byte
xxC5
Timer T2 Autoload Register T2RB
Upper Byte
xxC6
Timer T2 Control Register
xxC7
WATCHDOG Service Register
(Reg:WDSVR)
xxC8
MIWU Edge Select Register
(Reg:WKEDG)
xxC9
MIWU Enable Register (Reg:WKEN)
xxCA
MIWU Pending Register (Reg:WKPND)
xxCB
Reserved
xxCC
Reserved
xxCD to xxCF Reserved
Address
S/ADD REG
xxD0
xxD1
xxD2
xxD3
xxD4
xxD5
xxD6
xxD7
xxD8
xxD9
xxDA
xxDB
xxDC
xxDD to xxDF
xxE0 to xxE5
xxE6
xxE7
xxE8
xxE9
xxEA
xxEB
xxEC
xxED
xxEE
xxEF
xxF0 to xxFB
xxFC
xxFD
xxFE
xxFF
0100 to 017F
Contents
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D
Reserved
Reserved
Timer T1 Autoload Register T1RB
Lower Byte
Timer T1 Autoload Register T1RB
Upper Byte
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1RA
Lower Byte
Timer T1 Autoload Register T1RA
Upper Byte
CNTRL Control Register
PSW Register
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
S Register
On-Chip 128 RAM Bytes
Reading memory locations 0070H–007FH (Segment 0) will return all ones.
Reading unused memory locations 0080H–00AFH (Segment 0) will return
undefined data. Reading memory locations from other unused Segments
(i.e., Segment 2, Segment 3, … etc.) will return undefined data.
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