COP888EK Datasheet, PDF (23/46 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 8k Memory, Comparator, and Single-slope A/D Capability

Analog Function Block (Continued)
This device contains an analog function block with the intent
to provide a function which allows for single slope, low cost,
A/D conversion of up to 6 channels. See Application Note
983, Simple, Cost Effective A/D Conversion using
COP888EK, for further information on this application.
CMPSL REGISTER (ADDRESS X’00B7)
CMPT2B CMPISEL2 CMPISEL1 CMPISEL0 CMPOE CSEN CMPEN CMPNEG
Bit 7
Bit 0
The CMPSL register contains the following bits:
CMPT2B
Selects the timer T2B input to be driven di-
rectly by the comparator output. If the com-
parator is disabled (CMPEN = 0), this func-
tion is disabled, i.e., the T2B input is
connected to Port L5.
CMPISEL0/1/2 Will select one of seven possible sources
(I0/I2/I3/I4/I5/I6/internal reference) as a
positive input to the comparator (see Table
3 for more information.) Power savings can
be realized by deselecting the internal ref-
erence when it is not in actual use.
CMPOE
Enables the comparator output to either pin
I3 or pin I7 (“1” = enable) depending on the
value of CMPISEL0/1/2.
CSEN
Enables the internal constant current
source. This current source provides a
nominal 20 µA constant current at the I1
pin. This current can be used to ensure a
linear charging rate on an external capaci-
tor. This bit has no affect and the current
source is disabled if the comparator is not
enabled (CMPEN = 0).
CMPEN
Enable the comparator (“1” = enable).
CMPNEG
Will drive I1 to a low level. This bit can be
used to discharge an external capacitor.
This bit is disabled if the comparator is not
enabled (CMPEN = 0).
The Comparator Select Register is cleared on RESET (the
comparator is disabled). To save power the program should
also disable the comparator before the µC enters the HALT/
IDLE modes. Disabling the comparator will turn off the con-
stant current source and the V_CC/2 reference, disconnect the
comparator output from the T2B input and pin I3 or I7 and re-
move the low on I1 caused by CMPNEG.
It is often useful for the user’s program to read the result of
a comparator operation. Since I1 is always selected to be
COMPIN− when the comparator is enabled (CMPEN = 1),
the comparator output can be read internally by reading bit 1
(CMPRD) of register PORTI (RAM address 0 x D7).
The following table lists the comparator inputs and outputs
vs. the value of the CMPISEL0/1/2 bits. The output will only
be driven if the CMPOE bit is set to 1.
TABLE 3. Comparator Input Selection
CMPISEL2
0
0
0
0
1
1
1
1
Control Bit
CMPISEL1
0
0
1
1
0
0
1
1
CMPISEL0
0
1
0
1
0
1
0
1
Comparator Input Source
Neg. Input
Pos. Input
I1
I2
I1
I2
I1
I3
I1
I0
I1
I4
I1
I5
I1
I6
I1
V_CC/2 Ref.
Comparator
Output
I3
I7
I7
I7
I7
I7
I7
I7
RESET
The state of the Comparator Block immediately after RESET
is as follows:
1. The CMPSL Register is set to all zeros
2. The Comparator is disabled
3. The Constant Current Source is disabled
4. CMPNEG is turned off
5. The Port I inputs are electrically isolated from the com-
parator
6. The T2B input is as normally selected by the T2CNTRL
Register
7. CMPISEL0–CMPISEL2 are set to zero
8. All Port I inputs are selected to the default digital input
mode
The comparator outputs have the same specification as
Ports L and G except that the rise and fall times are sym-
metrical.
Interrupts
Each device supports eleven vectored interrupts. Interrupt
sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L
Wakeup, Software Trap, MICROWIRE/PLUS, and External
Input.
All interrupts force a branch to location 00FF Hex in program
memory. The VIS instruction may be used to vector to the
appropriate service routine from location 00FF Hex.
The Software trap has the highest priority while the default
VIS has the lowest priority.
Each of the 11 maskable inputs has a fixed arbitration rank-
ing and vector.
Figure 13 shows the Interrupt Block Diagram.
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