COP87L88GG Datasheet, PDF (8/42 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable OTP Microcontroller with UART and Three Multi-Function Timers

Pin Descriptions (Continued)
Note that the chip will be placed in the HALT mode by writ-
ing a ‘‘1’’ to bit 7 of the Port G Data Register Similarly the
chip will be placed in the IDLE mode by writing a ‘‘1’’ to bit 6
of the Port G Data Register
Writing a ‘‘1’’ to bit 6 of the Port G Configuration Register
enables the MICROWIRE PLUS to operate with the alter-
nate phase of the SK clock The G7 configuration bit if set
high enables the clock start up delay after HALT when the
R C clock configuration is used
Config Reg
Data Reg
G7
CLKDLY
HALT
G6
Alternate SK
IDLE
Port G has the following alternate features
G0 INTR (External Interrupt Input)
G2 T1B (Timer T1 Capture Input)
G3 T1A (Timer T1 I O)
G4 SO (MICROWIRE Serial Data Output)
G5 SK (MICROWIRE Serial Clock)
G6 SI (MICROWIRE Serial Data Input)
Port G has the following dedicated functions
G1 WDOUT WATCHDOG and or Clock Monitor dedicat-
ed output
G7 CKO Oscillator dedicated output or general purpose
input
Port C is an 8-bit I O port The 40-pin device does not have
a full complement of Port C pins The unavailable pins are
not terminated A read operation for these unterminated
pins will return unpredicatable values
Port I is an eight-bit Hi-Z input port
Port I1 – I3 are used for Comparator 1 Port I4–I6 are used
for Comparator 2
The Port I has the following alternate features
I1 COMP1bIN (Comparator 1 Negative Input)
I2 COMP1aIN (Comparator 1 Positive Input)
I3 COMP1OUT (Comparator 1 Output)
I4 COMP2bIN (Comparator 2 Negative Input)
I5 COMP2aIN (Comparator 2 Positive Input)
I6 COMP2OUT (Comparator 2 Output)
Port D is a recreated 8-bit output port that is preset high
when RESET goes low The user can tie two or more D port
outputs (except D2) together in order to get a higher drive
Functional Description
The architecture of the device is modified Harvard architec-
ture With the Harvard architecture the control store pro-
gram memory (ROM) is separated from the data store mem-
ory (RAM) Both ROM and RAM have their own separate
addressing space with separate address buses The archi-
tecture though based on Harvard architecture permits
transfer of data from ROM to RAM
CPU REGISTERS
The CPU can do an 8-bit addition subtraction logical or
shift operation in one instruction (t_c) cycle time
There are six CPU registers
A is the 8-bit Accumulator Register
PC is the 15-bit Program Counter Register
PU is the upper 7 bits of the program counter (PC)
PL is the lower 8 bits of the program counter (PC)
B is an 8-bit RAM address pointer which can be optionally
post auto incremented or decremented
X is an 8-bit alternate RAM address pointer which can be
optionally post auto incremented or decremented
SP is the 8-bit stack pointer which points to the subroutine
interrupt stack (in RAM) The SP is initialized to RAM ad-
dress 06F with reset
S is the 8-bit Data Segment Address Register used to ex-
tend the lower half of the address range (00 to 7F) into 256
data segments of 128 bytes each
All the CPU registers are memory mapped with the excep-
tion of the Accumulator (A) and the Program Counter (PC)
PROGRAM MEMORY
The program memory consists of 16 kbytes of OTP
EPROM These bytes may hold program instructions or con-
stant data (data tables for the LAID instruction jump vectors
for the JID instruction and interrupt vectors for the VIS in-
struction) The program memory is addressed by the 15-bit
program counter (PC) All interrupts in the devices vector to
program memory location 0FF Hex
The device can be configured to inhibit external reads of the
program memory This is done by programming the Security
Byte
SECURITY FEATURE
The program memory array has an associate Security Byte
that is located outside of the program address range This
byte can be addressed only from programming mode by a
programmer tool
Security is an optional feature and can only be asserted
after the memory array has been programmed and verified
A secured part will read all 00(hex) by a programmer The
part will fail Blank Check and will fail Verify operations A
Read operation will fill the programmer’s memory with
00(hex) The Security Byte itself is always readable with val-
ue of 00(hex) if unsecure and FF(hex) if secure
DATA MEMORY
The data memory address space includes the on-chip RAM
and data registers the I O registers (Configuration Data
and Pin) the control registers the MICROWIRE PLUS SIO
shift register and the various registers and counters asso-
ciated with the timers (with the exception of the IDLE timer)
Data memory is addressed directly by the instruction or indi-
rectly by the B X SP pointers and S register
The data memory consists of 512 bytes of RAM Sixteen
bytes of RAM are mapped as ‘‘registers’’ at addresses 0F0
to 0FF Hex These registers can be loaded immediately
and also decremented and tested with the DRSZ (decre-
ment register and skip if zero) instruction The memory
pointer registers X SP B and S are memory mapped into
this space at address locations 0FC to 0FF Hex respective-
ly with the other registers being available for general usage
The instruction set permits any bit in memory to be set
reset or tested All I O and registers (except A and PC) are
memory mapped therefore I O bits and register bits can be
directly and individually set reset and tested The accumu-
lator (A) bits can also be directly and individually tested
Note RAM contents are undefined upon power-up
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