COP87L88GG Datasheet, PDF (14/42 Pages) National Semiconductor (TI) – 8-Bit One-Time Programmable OTP Microcontroller with UART and Three Multi-Function Timers

Timers (Continued)
The timer mode control bits (TxC3 TxC2 and TxC1) are detailed below
TxC3
0
0
1
1
0
1
0
1
TxC2
0
0
0
0
1
1
1
1
TxC1
0
1
1
0
0
0
1
1
Timer Mode
MODE 2 (External
Event Counter)
MODE 2 (External
Event Counter)
MODE 1 (PWM)
TxA Toggle
MODE 1 (PWM)
No TxA Toggle
MODE 3 (Capture)
Captures
TxA Pos Edge
TxB Pos Edge
MODE 3 (Capture)
Captures
TxA Pos Edge
TxB Neg Edge
MODE 3 (Capture)
Captures
TxA Neg Edge
TxB Pos Edge
MODE 3 (Capture)
Captures
TxA Neg Edge
TxB Neg Edge
Interrupt A
Source
Timer
Underflow
Timer
Underflow
Autoreload
RA
Autoreload
RA
Pos TxA
Edge or
Timer
Underflow
Pos TxA
Edge or
Timer
Underflow
Neg TxA
Edge or
Timer
Underflow
Neg TxA
Edge or
Timer
Underflow
Interrupt B
Source
Pos TxB
Edge
Pos TxB
Edge
Autoreload
RB
Autoreload
RB
Pos TxB
Edge
Neg TxB
Edge
Pos TxB
Edge
Neg TxB
Edge
Timer
Counts On
TxA
Pos Edge
TxA
Neg Edge
t_c
t_c
t_c
t_c
t_c
t_c
Power Save Modes
The device offers the user two power save modes of opera-
tion HALT and IDLE In the HALT mode all microcontroller
activities are stopped In the IDLE mode the on-board oscil-
lator circuitry the WATCHDOG logic the Clock Monitor and
timer T0 are active but all other microcontroller activities are
stopped In either mode all on-board RAM registers I O
states and timers (with the exception of T0) are unaltered
HALT MODE
The device can be placed in the HALT mode by writing a
‘‘1’’ to the HALT flag (G7 data bit) All microcontroller activi-
ties including the clock and timers are stopped The
WATCHDOG logic is disabled during the HALT mode How-
ever the clock monitor circuitry if enabled remains active
and will cause the WATCHDOG output pin (WDOUT) to go
low If the HALT mode is used and the user does not want
to activate the WDOUT pin the Clock Monitor should be
disabled after the device comes out of reset (resetting the
Clock Monitor control bit with the first write to the WDSVR
register) In the HALT mode the power requirements of the
device are minimal and the applied voltage (V_CC) may be
decreased to V_r (V_r e 2 0V) without altering the state of the
machine
The device supports three different ways of exiting the
HALT mode The first method of exiting the HALT mode is
with the Multi-Input Wakeup feature on the L port The sec-
ond method is with a low to high transition on the CKO (G7)
pin This method precludes the use of the crystal clock con-
figuration (since CKO becomes a dedicated output) and so
may be used with an RC clock configuration The third
method of exiting the HALT mode is by pulling the RESET
pin low
Since a crystal or ceramic resonator may be selected as the
oscillator the Wakeup signal is not allowed to start the chip
running immediately since crystal oscillators and ceramic
resonators have a delayed start up time to reach full ampli-
tude and frequency stability The IDLE timer is used to gen-
erate a fixed delay to ensure that the oscillator has indeed
stabilized before allowing instruction execution In this case
upon detecting a valid Wakeup signal only the oscillator
circuitry is enabled The IDLE timer is loaded with a value of
256 and is clocked with the t_c instruction cycle clock The t_c
clock is derived by dividing the oscillator clock down by a
factor of 10 The Schmitt trigger following the CKI inverter
on the chip ensures that the IDLE timer is clocked only
when the oscillator has a sufficiently large amplitude to
meet the Schmitt trigger specifications This Schmitt trigger
is not part of the oscillator closed loop The startup timeout
from the IDLE timer enables the clock signals to be routed
to the rest of the chip
If an RC clock option is being used the fixed delay is intro-
duced optionally A control bit CLKDLY mapped as config-
uration bit G7 controls whether the delay is to be intro-
duced or not The delay is included if CLKDLY is set and
excluded if CLKDLY is reset The CLKDLY bit is cleared on
reset
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