DP83256 Datasheet, PDF (76/144 Pages) National Semiconductor (TI) – PLAYERa+™ Device (FDDI Physical Layer Controller)

5 0 Registers (Continued)
5 32 CMT CONDITION COMPARISON REGISTER (CMTCCR)
The CMT Condition Comparison Register (CMTCR) ensures that the Control Bus must first read a bit modified by the PLAYERa
device before it can be written to by the Control Bus Interface
The current state of the CMT Condition Register (CMTCR) is automatically written into the CMT Condition Comparison Register
(CMTCR) (i e CMTCCR e CMTCR) during a Control Bus Interface read-cycle of CMTCR
During a Control Bus Interface write cycle the PLAYERa device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
Control Register (ICR) to 1 and disallow the setting or clearing of a bit within the CMTCR when the value of a bit in the CMTCR
differs from the value of the corresponding bit in the CMT Condition Comparison Register
ACCESS RULES
ADDRESS
1Fh
READ
Always
WRITE
Always
D7
TCOC
D6
STEC
D5
RES
D4
RES
D3
RES
D2
RES
D1
RES
D0
RES
Bit Symbol
Description
D0-D5 RES
RESERVED Reserved for future use
D6
STEC SCRUB TIMER EXPIRED COMPARISON The comparison bit for the Scrub Timer Expire bit (STE) of the CMT
Condition Register (CMTCR)
D7
TCOC TRIGGER CONDITION OCCURRED COMPARISON The comparison bit for the Trigger Condition Occurred
(TCO) bit of the CMT Condition Register (CMTCR)
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