DP83256 Datasheet, PDF (1/144 Pages) National Semiconductor (TI) – PLAYERa+™ Device (FDDI Physical Layer Controller)

PRELIMINARY
October 1994
DP83256 56-AP 57
PLAYER^{a TM} Device (FDDI Physical Layer Controller)
General Description
The DP83256 56-AP 57 Enhanced Physical Layer Control-
ler (PLAYERa device) implements one complete Physical
Layer (PHY) entity as defined by the Fiber Distributed Data
Interface (FDDI) ANSI X3T9 5 standard
The PLAYERa device integrates state of the art digital
clock recovery and improved clock generation functions to
enhance performance eliminate external components and
remove critical layout requirements
FDDI Station Management (SMT) is aided by Link Error
Monitoring support Noise Event Timer (TNE) support Op-
tional Auto Scrubbing support an integrated configuration
switch and built-in functionality designed to remove all strin-
gent response time requirements such as PC React and
CF React
Features
Y _{Single chip FDDI Physical Layer (PHY) solution}
Y _{Integrated Digital Clock Recovery Module provides en-}
hanced tracking and greater lock acquisition range
Y _{Integrated Clock Generation Module provides all neces-}
sary clock signals for an FDDI system from an external
12 5 MHz reference
Y _{Alternate PMD Interface (DP83256-AP 57) supports}
UTP twisted pair FDDI PMDs with no external clock re-
covery or clock generation functions required
Y _{No External Filter Components}
Y _{Connection Management (CMT) Support (LEM TNE}
PC React CF React Auto Scrubbing)
Y _{Full on-chip configuration switch}
Y _{Low Power CMOS-BIPOLAR design using a single 5V}
supply
Y _{Full duplex operation with through parity}
Y _{Separate management interface (Control Bus)}
Y _{Selectable Parity on PHY-MAC Interface and Control}
Bus Interface
Y _{Two levels of on-chip loopback}
Y _{4B 5B encoder decoder}
Y _{Framing logic}
Y _{Elasticity Buffer Repeat Filter and Smoother}
Y _{Line state detector generator}
Y _{Supports single attach stations dual attach stations}
and concentrators with no external logic
Y _{DP83256 for SAS DAS single path stations}
Y _{DP83257 for SAS DAS single dual path stations}
Y _{DP83256-AP for SAS DAS single path stations that re-}
quire the alternate PMD interface
TL F 11708 – 1
FIGURE 1-1 FDDI Chip Set Overview
TRI-STATE is a registered trademark of National Semiconductor Corporation
BMACTM BSITM CDDTM CDLTM CRDTM CYCLONETM MACSITM PLAYERTM PLAYERaTM and TWISTERTM are trademarks of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 11708
RRD-B30M115 Printed in U S A