DP83256 Datasheet, PDF(53/144 Page) National Semiconductor (TI) – PLAYERa+™ Device (FDDI Physical Layer Controller)

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DP83256 Datasheet, PDF (53/144 Pages) National Semiconductor (TI) – PLAYERa+™ Device (FDDI Physical Layer Controller)

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5 0 Registers (Continued)

5 9 CURRENT RECEIVE STATE REGISTER (CRSR)

The Current Receive State Register represents the current line state being detected by the Receiver Block When the Receiver

Block recognizes a new Line State the bits corresponding to the previous line state are cleared and the bits corresponding to

the new line state are set

During the reset process (ERSTeGND) the Receiver Block is forced to Line State Unknown (i e the Line State Unknown bit

(LSU) is set to 1)

Note Users are discouraged from writing to this register An attempt to write into this register will cause the PLAYERa device to ignore the Control Bus write cycle

and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1

ACCESS RULES

ADDRESS

08h

READ

Always

WRITE

Write Reject

RES

LSU

LS2

LS1

LS0

Bit

D1 D2

Symbol

LS0 LS1

LS2

LSU

D4-D7 RES

Description

LINE STATEk0 1 2l These bits represent the current Line State being detected by the Receiver Block

Once the Receiver Block recognizes a new line state the bits corresponding to the previous line state are

cleared and the bits corresponding to the new line state are set

LS2 LS1 LS0

0 0 0 Active Line State (ALS) Received a JK symbol pair (11000 10001) possibly followed

by data symbols

0 0 1 Idle Line State (ILS) Received a minimum of two consecutive Idle symbol pairs

(11111 11111)

0 1 0 No Signal Detect (NSD) The Signal Detect (SD) has been deasserted indicating that

the PLAYERa device is not receiving data from the PMD receiver or that clock detect is

not being received from the Clock Recovery Module SD is ignored during internal

loopback

Note NSD is the default value when the device is in Stop mode However while in Stop mode certain data

patterns entering the Receiver Block may cause the PLAYERa to set LS0 Therefore the user may see

either the NSD (010) or Reserved Value (011) during Stop mode

0 1 1 Reserved Reserved for future use

1 0 0 Master Line State (MLS) Received a minimum of 8 consecutive Halt-Quiet symbol

pairs (00100 00000)

1 0 1 Halt Line State (HLS) Received a minimum of 8 consecutive Halt symbol pairs

(00100 00100)

1 1 0 Quiet Line State (QLS) Received a minimum of 8 consecutive Quiet symbol pairs

(00000 00000)

1 1 1 Noise Line State (NLS) Detected a minimum of 16 noise events Refer to the Receiver

Block description for further information on noise events

LINE STATE UNKNOWN The Receiver Block has not detected the minimum conditions to enter a known

line state When the Line State Unknown bit is set LSk2 0l represent the most recently known line state

RESERVED Reserved for future use

Note Users are discouraged from using these bits The reserved bits are reset to 0 during the reset process They may be set or cleared

without any effects to the functionality of the PLAYERa device

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