LP3936 Datasheet, PDF (7/20 Pages) National Semiconductor (TI) – Lighting Management System for Six White LEDs and One RGB or FLASH LED

Logic Interface Characteristics
(1.8V ≤ V_{DD_IO} ≤ V_DD1,2) (Note 11)
Symbol
Parameter
Conditions
Min
LOGIC INPUTS DI, SCL, NRST, RGB_EN, CS, MW_SEL
V_IL
Input Low Level
V_IH
Input High Level
I_I
Logic Input Current
f_SCL
Clock Frequency
I²C Mode
MicroWire Mode
V_{DD_IO} − 0.5
−1.0
LOGIC OUTPUTS DO, CS
V_OL
Output Low Level
I_{DO, CS} = 3 mA
V_OH
Output High Level
I_DO = − 3 mA
I_L
Output Leakage Current V_DO = 2.8V
V_{DD_IO} − 0.6
Note 11: In I²C mode operating ratings are limited to 3.0V ≤ V_DD1,2 ≤ 4.5V and –20˚C ≤ T_A ≤ +85˚C.
Typ
0.3
V_{DD_IO} − 0.3
Max
0.5
1.0
400
8
0.6
1.0
Units
V
V
µA
kHz
MHz
V
V
µA
Control Interface
The LP3936 supports two different interfaces modes:
1) MicroWire/SPI interface
2) I²C compatible interface
User can define the interface by MW_SEL pin. The pin
configuration will also change depending on which interface
is selected. The following table shows the selections for both
interface modes.
MW_SEL
Interface
1
MicroWire/SPI
0
I²C Compatible
Pin Configuration
SCL
(clock)
DI
(data in)
DO
(data out)
CS
(chip select)
SCL
CS = SDA
(clock)
(data in/out)
Comment
Use pull up resistor for SCL
Use pull up resistor for SDA
MicroWire/SPI Interface
The Microwire transmission consists of 16-bit Write and
Read Cycles. One cycle consists of 7 Address bits, 1 Read/
Write (R/W) bit and 8 Data bits. Read is done in two cycles:
address is provided in the first cycle and the data is sent out
on the next cycle. R/W bit high state defines a Write Cycle
and low defines a Read Cycle. DO output is normally in
high-impedance state and it is active only during Write and
Read Cycles. A pull-up or pull-down resistor may be needed
in DO line if a floating logic signal can cause unintended
current consumption in other circuits where DO is con-
nected.
The Address and Data are transmitted MSB first. The Chip
Select signal CS must be low during the Cycle transmission.
CS resets the interface when high and it has to be taken high
between successive Cycles. Data is clocked in on the rising
edge of the SCL clock signal, while data is clocked out on the
falling edge of SCL.
The MicroWire interface mode can also support SPI inter-
face. The difference with normal SPI interface is that in
LP3936 the Read operation from a new address needs two
read cycles. If repetitive reads are made from the same
address, a correct value is obtained on every read cycle.
MicroWire Write Cycle
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