LP3929 Datasheet, PDF (7/12 Pages) National Semiconductor (TI) – High Speed Bi-Directional Level Shifter and Ultra Low-Dropout CMOS Voltage Regulator and Line

Electrical Characteristics Unless otherwise specified: C_VBAT = 1 µF, I_OUT = 1 mA, C_VDDB = 1 µF, C_VDDA =
1 µF. Typical values and limits appearing in standard typeface apply for T_A = 25˚C. Limits appearing in boldface type apply
over the entire ambient temperature range for operation, −30˚C to +85˚C. (Notes 3, 4)
Symbol
Parameter
Supply Current
I_DD
Supply Current
I_DDZ
Supply Current — Shutdown
C_OUT
Output Capacitance (Note 15)
Conditions
All Channels Static: A → B
mode, LDO unloaded
EN = V_SS
B (card) port
V_BAT
V_DDA
V_BAT
V_DDA
Min Typ Max Units
4
7
mA
95 200
µA
0.1
2
µA
0.2
2
µA
15
20
pF
Level Shifter AC Switching Characteristics Unless otherwise specified: C_VBAT = 1 µF, I_OUT = 1
mA, C_VDDB = 1 µF, C_VDDA = 1 µF. Typical values and limits appearing in standard typeface apply for T_A = 25˚C. Limits ap-
pearing in boldface type apply over the entire ambient temperature range for operation, −30˚C to +85˚C. (Notes 3, 5, 15, 16)
Symbol
Parameter
t_PLH
Propagation Delay A to B or B to A
Propagation Delay CLK_A to fCLK_A
t_PHL
Propagation Delay A to B or B to A
t_RISE
t_FALL
t_SKEW
t_EN
t_DIS
t_TA
Propagation Delay CLK_A to fCLK_A
Rise Time A Side Output Figure 2
Rise Time B Side Output with ASIP Figure 2
Fall Time A Side Output Figure 2
Fall Time B Side Output with ASIP Figure 2
Skew between D0–D3, CLK and CMD outputs
(either edge)
Enable Time
Disable Time
Level-Shifter Direction Switch Response
(Turn Around) Time
Conditions
C_LB = 15 pF, C_LA = 20 pF,
50%-50%
C_LA = 20 pF, 50%-50%
C_LB = 15 pF, C_LA = 20 pF,
50%-50%
C_LA = 20 pF, 50%-50%
C_LA = 20 pF, 20%-70%
C_LB = 15 pF, 20%-70%
C_LA = 20 pF, 20%-70%
C_LB = 15 pF, 20%-70%
Min Typ Max Units
3
7
ns
5
14
ns
3
7
ns
5
14
ns
1.1
3
ns
1.6
3
ns
1.0
3
ns
1.9
3
ns
<0.5 1.0
ns
30 200
µs
18
50
ns
13
20
ns
7
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