DS90LV804_07 Datasheet, PDF (7/10 Pages) National Semiconductor (TI) – 4-Channel 800 Mbps LVDS Buffer/Repeater

OUTPUT INTERFACING
The DS90LV804 outputs signals that are compliant to the LVDS standard. Their outputs can be DC-coupled to most common
differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers and assumes
that the receivers have high impedance inputs. While most differential receivers have a common mode input range that can ac-
comodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to implementing the
suggested interface implementation.
20156734
Typical DS90LV804 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
TYPICAL PERFORMANCE CHARACTERISTICS
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Dynamic power supply current was measured while running a clock or PRBS
2²³-1 pattern with all 4 channels active. V_CC = 3.3V, T_A = +25°C, V_ID = 0.5V,
V_CM = 1.2V
Power Supply Current vs. Bit Data Rate
Packaging Information
The Leadless Leadframe Package (LLP) is a leadframe
based chip scale package (CSP) that may enhance chip
speed, reduce thermal impedance, and reduce the printed
circuit board area required for mounting. The small size and
very low profile make this package ideal for high density PCBs
used in small-scale electronic applications such as cellular
phones, pagers, and handheld PDAs. The LLP package is
offered in the no Pullback configuration. In the no Pullback
configuration the standard solder pads extend and terminate
at the edge of the package. This feature offers a visible solder
fillet after board mounting.
The LLP has the following advantages:
• Low thermal resistance
• Reduced electrical parasitics
• Improved board space efficiency
• Reduced package height
• Reduced package mass
For more details about LLP packaging technology, refer to
applications note AN-1187, "Leadless Leadframe Package"
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