LM1291 Datasheet, PDF (6/12 Pages) National Semiconductor (TI) – Video PLL System for Continuous-Sync Monitors

Pin Descriptions (Continued)
Pin 11 - H HV SYNC OUT The sync processor outputs
active-low H HV sync derived from the active sync input
(pin 9 or pin 12) Pin 11 stays low in the absence of sync
input See Figure 4 for the output schematic
Pin 12 - H HV SYNC IN This pin accepts AC-coupled H or
composite sync of either polarity For best noise immunity a
resistor of 2 kX or less should be connected from the input
side of the coupling cap to ground See Figure 8 for the
input schematic
Pin 13 - H HV POL OUT A low logic level indicates active-
high H HV sync to pin 12 a high level indicates active-low
Pin 13 stays low in the absence of H HV sync See Figure 9
for the output schematic
Pin 14 - H DR DUTY CNTL A DC voltage applied to this pin
sets the duty cycle of the horizontal drive output (pin 20)
with a range of approximately 30%–70% 2V sets the duty
cycle to 50% See Figure 10 for the input schematic
Pin 15 - H DRIVE EN A low logic level input enables H
DRIVE OUT (pin 20) See Figure 11 for the input schematic
Pin 16 - X-RAY SHUTDOWN This pin is for monitoring CRT
anode voltage If the input voltage exceeds an internal
threshold H DRIVE OUT (pin 20) is latched high and VIDEO
MUTE (pin 3) is latched low V_CC has to be reduced to be-
low approximately 2V to clear the latched condition i e
power must be turned off See Figure 12 for the input sche-
matic
Pin 17 - V SYNC OUT The sync processor outputs active-
low V sync derived from the active sync input (pin 8 pin 9 or
pin 12) Pin 17 stays low in the absence of sync input See
Figure 4 for the output schematic
Pin 18 - FLYBACK IN Input pin for phase detector 2 For
best operation the flyback peak should be at least 5V but
not greater than V_CC Any pulse width greater than 1 5 ms is
acceptable See Figure 13 for the input schematic
Pin 19 - V POL OUT A low logic level indicates active-high
V sync to pin 8 a high level indicates active-low Pin 19
stays low in the absence of V sync See Figure 9 for the
output schematic
Pin 20 - H DRIVE OUT This is an open-collector output
which provides the drive pulse for the high power deflection
circuit The pulse duty cycle is controlled by pin 14 Polarity
convention Horizontal deflection output transistor is on
when H DRIVE OUT is low See Figure 5 for the output
schematic
Pin 21 - GND System ground For best jitter performance
all LM1291 filter components and bypass capacitors should
be connected to this pin via short paths
Pin 22 - PHASE DET 2 CAP The low-pass filter cap for the
output of phase detector 2 is connected from this pin to pin
21 (GND) via a short path
Pin 23 - H DRlVE PHASE A DC control voltage applied to
this pin sets the phase of the flyback pulse with respect to
the leading edge of H sync See Figure 14 for the input
schematic
Pin 24 - V CAP A capacitor is connected from this pin to
ground for detecting the polarity and existence of V sync at
pin 8
Pin 25 - FVC CAP 2 Secondary FVC filter pin C_FVC2 is
connected from this pin to ground The width of the VIDEO
MUTE (pin 3) pulse is controlled by the time constant differ-
ence between the filters at pins 25 and 26
Pin 26 - FVC CAP 1 Primary FVC filter pin C_FVC1 is con-
nected from this pin to pin 21 (GND) via a short path The
voltage at this pin is buffered to pin 27 (FVC OUT)
Pin 27 - FVC OUT Buffered output of the Frequency-to-
Voltage Converter which sets the VCO center frequency
through an external resistor to pin 28 Care should be taken
when further loading this pin since during the vertical inter-
val it presents a high output impedance Excessive loading
can cause top-of-screen phase recovery problems
Pin 28 - PD1 OUT VCO IN Phase detector 1 has a gated
charge pump output which requires an external low-pass
filter For best jitter performance the filter should be
grounded to pin 21 (GND) via a short path If a voltage
source is applied to this pin the phase detector is disabled
and the VCO can be controlled directly
Application Hints
1 Phase control for geometry correction
Pin 23 (H DRlVE PHASE) is designed to control static phase
(picture horizontal position) while pin 22 (PHASE DET 2
CAP) controls dynamic phase for geometry correction With
the use of both pins 22 and 23 complete control of static
and dynamic phase can be achieved To accomplish this
the low-pass filter cap at pin 22 is not grounded but is con-
nected instead to a modulating AC voltage source The cap
then functions both as a low-pass filter (for phase detector
2) and as an input coupling cap (for the AC source)
2 Programmable frequency ramping
H frequency transitions from high to low present a special
problem for deflection output stages without current limiting
lf during such a transition the output transistor on-time in-
creases excessively before the Ba voltage has decreased
to its final level then the deflection inductor current ramps
too high and the induced flyback pulse can exceed the
breakdown voltage BV_CEX of the output transistor To pre-
vent this the rate of change of the VCO frequency must be
limited
Consider a scanning mode transition at t e 0 from f₁ to f₂
The VCO frequency as a function of time f_VCO(t) is de-
scribed by the equation
f_VCO(t) ^j f₁ a (f₂ b f₁)(1 b exp(bt u))
where u e 40 c 10³ c C_FVC1
The above equation can be used to predict VCO behavior
during frequency transitions but in practice the value of
C_FVC1 is most easily determined empirically In general
large vaIues minimize the chance of exceeding BV_CEX but
generate long PLL capture times
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