LM1291 Datasheet, PDF (5/12 Pages) National Semiconductor (TI) – Video PLL System for Continuous-Sync Monitors

Block Diagram
FIGURE 3
TL H 12323 – 3
Pin Descriptions
See Figures 4 through 15 for input and output schematics
Pin 1 - CLAMP CNTL This low-impedance current-mode
input pin is internally biased to 2V The direction of current
sets the pulse position (back porch or sync-tip) while the
current magnitude sets the pulse width In a typical applica-
tion a control voltage of 0V–4V is applied to this pin
through a 15 kX resistor A voltage below 2V positions the
pulse on the back porch of the horizontal sync pulse and
decreasing voltage narrows the pulse A voltage above 2V
sets the pulse on the H sync-tip (slightly delayed from the
leading edge) and increasing voltage narrows the pulse At
the boundary of the switchover between the two modes
there is a narrow region of uncertainty resulting in oscilla-
tion which should be no problem in most applications
When there is no H sync in sync-tip mode the clamp pulse
is generated by the VCO at the frequency preset by pin 5
(f_MIN) This feature is intended for use in On Screen Display
systems
Pin 2 - CLAMP PULSE Active-low clamp pulse output See
Figure 4 for the output schematic
Pin 3 - VIDEO MUTE This NPN open-collector output pro-
duces an active-low pulse when triggered by a step change
of H sync frequency See Figure 5 for the output schematic
Pin 4 - f_MAX A resistor from this pin to ground sets the
upper frequency limit of the VCO f_MAX is approximately
1 8 c 10⁹
Hz
(R_MAX a 500)
Pin 5 - f_MIN A resistor from this pin to ground sets the lower
frequency limit of the VCO f_MIN is approximately
7 5 c 10³ a ^{5 6 c 108} Hz
(R_MIN a 500)
Pin 6 - V_REF CAP This is the decoupling pin for the internal
8 2V reference It should be decoupled to pin 21 (GND) via
a short path with a cap of at least 470 mF
Pin 7 - V_CC 12V nominal power supply pin This pin should
be decoupled to pin 21 (GND) via a short path with a cap of
at least 47 mF
Pin 8 - V SYNC IN This pin accepts AC-coupled V sync of
either polarity The pin is internally biased at 5 2V its input
resistance is approximately 50 kX For best noise immunity
a resistor of 2 kX or less should be connected from the
input side of the coupling cap to ground See Figure 6 for
the input schematic
Pin 9 - COMP VIDEO IN The composite video sync stripper
is active only when no signal is present at pin 12 (H HV IN)
The signal to pin 9 must have negative-going sync tips
which are at least 0 14V below black level For best noise
immunity a resistor of 2 kX or less should be connected
from the input side of the coupling cap to ground See Fig-
ure 7 for the input schematic
Pin 10 - H HV CAP A capacitor is connected from this pin
to ground for detecting the polarity and existence of H HV
sync at pin 12
5