DS90CR486_06 Datasheet, PDF (6/18 Pages) National Semiconductor (TI) – 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)

C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
20025225
Tppos—Transmitter output pulse position (min and max)
RSKMD = ISI (Inter-symbol interference) + TPPOS(variance) + LVDS Source Clock Jitter (cycle to cycle)
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Note 8: Refer to transmitter datasheet for Cycle-to-cycle LVDS Output jitter specification.
Note 9: ISI is dependent on interconnect length; may be zero. Pre-emphasis in the transimitter is used to reduce the ISI. Refer to transmitter datasheet for more
information.
FIGURE 7. Receiver Skew Margin with DESKEW (RSKMD)
www.national.com
6