DS90CR486_06 Datasheet, PDF (3/18 Pages) National Semiconductor (TI) – 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)

Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
CLHT
LVCMOS/LVTTL Low-to-High Transition Time, (Figure 2), Rx
0.8
data out, (Note 5)
LVCMOS/LVTTL Low-to-High Transition Time, (Figure 2), Rx
0.7
clock out, (Note 5)
CHLT
LVCMOS/LVTTL High-to-Low Transition Time, (Figure 2), Rx
0.9
data out, (Note 5)
LVCMOS/LVTTL High-to-Low Transition Time, (Figure 2), Rx
0.8
clock out, (Note 5)
RCOP RxCLK OUT Period, (Figure 3)
7.518
T
RCOH RxCLK OUT High Time, (Figure 3)
f = 133 MHz
2.7
f = 100 MHz
3.8
f = 66 MHz
6.0
RCOL
RxCLK OUT Low Time, (Figure 3)
f = 133 MHz
2.7
f = 100 MHz
3.8
f = 66 MHz
6.0
RSRC RxOUT Data valid before RxCLK OUT, (Figure f = 133 MHz
2.0
3.5
3)
f = 100 MHz
3.0
4.7
f = 66 MHz
5.0
7.0
RHRC RxOUT Data valid after RxCLK OUT, (Figure f = 133 MHz
2.5
4.1
3)
f = 100 MHz
3.5
5.0
f = 66 MHz
6.0
8.0
RPDL
Receiver Propagation Delay - Latency, (Figure 4)
2(TCIP)+5
2(TCIP)+10
RPLLS Receiver Phase Lock Loop Set ,(Figure 5)
RPDD Receiver Powerdown Delay, (Figure 6)
RSKMD Receiver Skew Margin with Deskew, BAL=Low f = 133 MHz
275
(Figure 7), (Note 6)
f = 100 MHz
400
f = 66 MHz
500
RDR
Receiver Deskew Range
f = 133 MHz
−150
f = 100 MHz
−200
f = 66 MHz
−200
Max
Units
1.3
ns
1.0
ns
1.3
ns
1.0
ns
15.152
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2(TCIP)+15
ns
10
ms
1
µs
ps
ps
ps
+150
ps
+200
ps
+200
ps
Note 1: The I_IN parameter for the PD pin is not tested at 2.5V.
Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 3: Typical values are given for V_CC = 3.3V and T _A = +25°C.
Note 4: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except V_TH, V_TL and ΔV_ID).
Note 5: CLHT and CHLT are measurements of the receiver data outputs low-to-high and high-to-low time over the recommended frequency range. The limits
are based on bench characterization and Guaranteed By Design (GBD) using statistical analysis.
Note 6: Receiver Skew Margin with Deskew (RSKMD) is defined as the valid data sampling region at the receiver inputs. The DESKEW function will constrain
the receiver’s sampling strobes to the middle half of the LVDS bit and removes (adjusts for) fixed interconnect skew. This margin (RSKMD) allows for inter-symbol
interference (dependent on type/length of cable), Transmitter Pulse Position (TPPOS) variance, and LVDS clock jitter (TJCC).
RSKMD ≥ ISI + TPPOS(variance) + LVDS Source Clock Jitter (cycle to cycle). See Applications Information section for more details.
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