DS90CR486_06 Datasheet, PDF (4/18 Pages) National Semiconductor (TI) – 133MHz 48-Bit Channel Link Deserializer (6.384 Gbps)

AC Timing Diagrams
FIGURE 1. “Worst Case” Test Pattern
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O.
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FIGURE 2. DS90CR486 LVCMOS/LVTTL Output Load and Transition Times
FIGURE 3. DS90CR486 Setup/Hold and High/Low Times
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