COP888CF Datasheet, PDF (6/44 Pages) National Semiconductor (TI) – 8-Bit CMOS ROM Based Microcontrollers with 4k Memory and A/D Converter

DC Electrical Characteristics 988CF: (Continued)
0˚C ≤ T_A ≤ +70˚C unless otherwise specified
Parameter
Conditions
Allowable Sink/Source
Current per Pin
D Outputs (Sink)
All others
Maximum Input Current
without Latchup (Note 7)
T_A = 25˚C
RAM Retention Voltage, V_r
500 ns Rise
and Fall Time (Min)
Input Capacitance
Load Capacitance on D2
Min
Typ
Max
Units
15
mA
3
mA
±100
mA
2
V
7
pF
1000
pF
Note 2: Rate of voltage change must be less then 0.5 V/ms.
Note 3: Supply current is measured after running 2000 cycles with a square wave CKI input, CKO open, inputs at rails and outputs open.
Note 4: The HALT mode will stop CKI from oscillating in the RC and the Crystal configurations. Test conditions: All inputs tied to V_CC, L and G0–G5 configured as
outputs and set high. The D port set to zero. The A/D is disabled. V_REF is tied to AGND (effectively shorting the Reference resistor). The clock monitor is disabled.
A/D Converter Specifications
V_CC = 5V ±10% (V_SS − 0.050V) ≤ Any Input ≤ (V_CC + 0.050V)
Parameter
Conditions
Resolution
Reference Voltage Input
AGND = 0V
Absolute Accuracy
Non-Linearity
V_REF = V_CC
V_REF = V_CC
Deviation from the
Best Straight Line
Differential Non-Linearity
Input Reference Resistance
V_REF = V_CC
Common Mode Input Range (Note 8)
DC Common Mode Error
Off Channel Leakage Current
On Channel Leakage Current
A/D Clock Frequency (Note 6)
Conversion Time (Note 5)
Min
Typ
3
1.6
AGND
1
1
0.1
12
Max
8
V_CC
±1
±¹â„2
±¹â„2
4.8
V_REF
±¹â„4
1.67
Units
Bits
V
LSB
LSB
LSB
kΩ
V
LSB
µA
µA
MHz
A/D Clock
Cycles
Note 5: Conversion Time includes sample and hold time.
Note 6: See Prescaler description.
Note 7: Pins G6 and RESET are designed with a high voltage input network for factory testing. These pins allow input voltages greater than V_CC and the pins will
have sink current to V_CC when biased at voltages greater than V_CC (the pins do not have source current when biased at a voltage below V_CC). The effective resis-
tance to V_CC is 750Ω (typical). These two pins will not latch up. The voltage at the pins must be limited to less than 14V.
Note 8: For V_IN(−)≥V_IN(+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input. The diodes will forward conduct for analog
input voltages below ground or above the V_CC supply. Be careful, during testing at low V_CC levels (4.5V), as high level analog inputs (5V) can cause this input diode
to conduct — especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward bias of either diode. This means
that as long as the analog V_IN does not exceed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 V_DC to 5 V_DC input
voltage range will therefore require a minimum supply voltage of 4.950 V_DC over temperature variations, initial tolerance and loading. The voltage at any analog input
should be −0.3V to V_CC +0.3V.
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