CD4071BM Datasheet, PDF (6/8 Pages) National Semiconductor (TI) – Quad 2-Input OR, AND Buffered B Series Gate

Schematic Diagrams
CD4071B
TL F 5977–1
CD4081B
TL F 5977–4
of device shown
JeAaB
Logical ‘‘1’’ e High
Logical ‘‘0’’ e Low
All inputs protected by standard
CMOS protection circuit
TL F 5977 – 2
of device shown
JeAB
Logical ‘‘1’’ e High
Logical ‘‘0’’ e Low
All inputs protected by standard
CMOS protection circuit
TL F 5977 – 5
6