HPC36164 Datasheet, PDF(5/38 Page) National Semiconductor (TI)

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HPC36164 Datasheet, PDF (5/38 Pages) National Semiconductor (TI) – Silicon Schottky Barrier Diode

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A D Converter Specifications

VCC 5V g10% (VSS b 0 05V) s Any Input s (VCC a 0 05V) fC

Parameter

Conditions

20 MHz and Prescalar fC 12

Min

Typ

Max

Units

Resolution

Bits

Reference Voltage Input

Absolute Accuracy

Non-Linearity

Differential Non-Linearity

Input Reference Resistance

AGND 0V

VCC 5 5V VREF 5V

VCC 5V VREF 5V and

VCC 4 5V VREF 4 5V

VCC 5 5V VREF 5V

VCC 5V VREF 5V and

VCC 4 5V VREF 4 5V

VCC 5 5V VREF 5V

VCC 5V VREF 5V and

VCC 4 5V VREF 4 5V

VCC

LSB

Common Mode Input Range (Note 9)

DC Common Mode Error

AGND

VREF

LSB

Off Channel Leakage Current

On Channel Leakage Current

A D Clock Frequency (Note 8)

1 67

MHz

Conversion Time (Note 7)

12 5

A D Clock Cycles

Note 7 Conversion Time includes sample and hold time See following diagrams

Note 8 See Prescalar description

Note 9 For VIN( ) l VIN(a) the digital output code will be 0000 0000 Two on-chip diodes are tied to each analog input The diodes will forward conduct for analog

input voltages below ground or above the VCC supply Be careful during testing at low VCC levels (4 5V) as high level analog inputs (5 0V) can cause this input

diode to conduct especially at elevated temperatures and cause errors for analog inputs near full-scale The spec allows 50 mV forward bias of either diode This

means that as long as the analog VIN does not exceed the supply voltage by more than 50 mV the output code will be correct To achieve an absolute 0 VDC to

5 0VDC input voltage range will therefore require a minimum supply voltage of 4 950 VDC over temperature variations initial tolerance and loading

Timing Diagram

TL DD 9682 11

Note The trigger condition generated by the start conversion method selected by the SC bits requires one CK2 to propagate through before the trigger condition is

known Once the trigger condition is known the sample and hold will start at the next rising edge of ADCLK The figure shows worst case

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