HPC36164 Datasheet, PDF (26/38 Pages) National Semiconductor (TI) – Silicon Schottky Barrier Diode

A D Converter
The HPC46164 has an on-board eight-channel 8-bit Analog
to Digital converter Conversion is peformed using a succes-
sive approximation technique The A D converter cell can
operate in single-ended mode where the input voltage is
applied across one of the eight input channels (D0–D7) and
AGND or in differential mode where the input voltage is ap-
plied across two adjacent input channels The A D convert-
er will convert up to eight channels in single-ended mode
and up to four channel-pairs in differential mode
OPERATING MODES
The operating modes of the converter are selected by 4 bits
called ADMODE (CR2 4–7) see Table IV Associated with
the eight input channels in single-ended mode are eight re-
sult registers one for each channel The A D converter can
be programmed by software to convert on any specific
channel storing the result in the result register associated
with that channel It can also be programmed to stop after
one conversion or to convert continuously If a brief history
of the signal on any specific input channel is required the
converter can be programmed to convert on that channel
and store the consecutive results in each of the result regis-
ters before stopping As a final configuration in single-ended
mode the converter can be programmed to convert the sig-
nal on each input channel and store the result in its associ-
ated result register continuously
Associated with each even-odd pair of input channels in
differential mode of operation are four result register-pairs
The A D converter performs two conversions on the select-
ed pair of input channels One conversion is performed as-
suming the positive connection is made to the even channel
and the negative connection is made to the following odd
channel This result is stored in the result register associat-
ed with the even channel Another conversion is performed
assuming the positive connection is made to the odd chan-
nel and the negative connection is made to the preceding
even channel This result is stored in the result register as-
sociated with the odd channel This technique does not re-
quire that the programmer know the polarity of the input
signal If the even channel result register is nonzero (mean-
ing the odd channel result register is zero) then the input
signal is positive with respect to the odd channel If the odd
channel result register is non-zero (meaning the even chan-
nel result register is zero) then the input signal is positive
with respect to the even channel
The same operating modes for single-ended operation also
apply when the inputs are taken from channel-pairs in differ-
ential mode The programmer can configure the A D to con-
vert on any selected channel-pair and store the result in its
associated result register-pair then stop The A D can also
be programmed to do this continuously Conversion can
also be done on any channel-pair storing the result into four
result register-pairs for a history of the differential input Fi-
nally all input channel-pairs can be converted continuously
The final mode of operation suppresses the external ad-
dress data bus activity during the single conversion modes
These quiet modes of operation utilize the RDY function of
the HPC Core to insert wait states in the instruction being
executed in order to limit digital noise in the environment
due to external bus activity when addressing external mem-
ory The overall effect is to increase the accuracy of the
AD
CONTROL
The conversion clock supplied to the A D converter can be
selected by three bits in CR1 used as a prescaler on CKI
These bits can be used to ensure that the A D is clocked as
fast as possible when different external crystal frequencies
are used Controlling the starting of conversion cycles in
each of the operating modes can be done by four different
methods The method is selected by two bits called SC
(CR3 0 – 1) Conversion cycles can be initiated through soft-
ware by resetting a bit in a control register through hard-
ware by an underflow of Timer T2 or externally by a rising or
falling edge of a signal input on I7
INTERRUPTS
The A D converter can interrupt the HPC when it completes
a conversion cycle if one of the noncontinuous modes has
been selected If one of the cycle modes was selected then
the converter will request an interrupt after eight conver-
sions If one of the one-shot modes was selected then the
converter will request an interrupt after every conversion
When this interrupt is generated the HPC vectors to the on-
board peripheral interrupt vector location at address FFF2
The service routine must then determine if the A D convert-
er requested the interrupt by checking the A D done flag
which doubles as the A D interrupt pending flag
Analog Input and Source Resistance Considerations
Figure 27 shows the A D pin model for the HPC46164 in
single ended mode The differential mode has similar A D
pin model The leads to the analog inputs should be kept as
short as possible Both noise and digital clock coupling to
an A D input can cause conversion errors The clock lead
should be kept away from the analog input line to reduce
coupling The A D channel input pins do not have any inter-
nal output driver circuitry connected to them because this
circuitry would load the analog input singals due to output
buffer leakage current
The analog switch is closed only during the sample time
FIGURE 27 Port D Input Structure
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TL DD 9682 12