HPC36164 Datasheet, PDF (27/38 Pages) National Semiconductor (TI) – Silicon Schottky Barrier Diode

A D Converter (Continued)
TABLE IV A D Operating Modes
Mode 0 Single-ended single channel single result
register one-shot (default value on power-up)
Mode 1 Single-ended single channel single result
register continuous
Mode 2 Single-ended single channel multiple result
registers stop after 8
Mode 3 Single-ended multiple channel multiple result
registers continuous
Mode 4 Differential single channel-pair single result
register-pair one-shot
Mode 5 Differential single channel-pair single result
register-pair continuous
Mode 6 Differential single channel-pair multiple result
register-pairs stop after 4 pairs
Mode 7 Differential multiple channel-pair multiple
result register-pairs continuous
Mode 8
Single-ended single channel single result
register one-shot (default value on power-
up) quiet address data bus
Mode C Differential single channel-pair single result
register-pair one-shot quiet address data bus
Source impedances greater than 1 kX on the analog input
lines will adversely affect internal RC charging time during
input sampling As shown in Figure 27 the analog switch to
the capacitor array is closed only during the 2 A D cycle
sample time Large source impedances on the analog in-
puts may result in the capacitor array not being charged to
the correct voltage levels causing scale errors
If large source resistance is necessary the recommended
solution is to slow down the A D clock speed in proportion
to the source resistance The A D converter may be operat-
ed at the maximum speed for R_S less than 1 kX For R_S
greater than 1 kX A D clock speed needs to be reduced
For example with R_S 2 kX the A D converter may be
operated at half the maximum speed A D converter clock
speed may be slowed down by either increasing the A D
prescaler divide-by or decreasing the CKI clock frequency
The A D clock speed may be reduced to its minimum fre-
quency of 100 kHz
Universal Peripheral Interface
The Universal Peripheral Interface (UPI) allows the
HPC46164 to be used as an intelligent peripheral to another
processor The UPI could thus be used to tightly link two
HPC46164’s and set up systems with very high data ex-
change rates Another area of application could be where
an HPC46164 is programmed as an intelligent peripheral to
a host system such as the Series 32000 microprocessor
Figure 28 illustrates how an HPC46164 could be used as an
intelligent peripherial for a Series 32000-based application
The interface consists of a Data Bus (port A) a Read Strobe
(URD) a Write Strobe (UWR) a Read Ready Line (RDRDY)
a Write Ready Line (WRRDY) and one Address Input (UA0)
The data bus can be either eight or sixteen bits wide
The URD and UWR inputs may be used to interrupt the
HPC46164 The RDRDY and WRRDY outputs may be used
to interrupt the host processor
The UPI contains an Input Buffer (IBUF) an Output Buffer
(OBUF) and a Control Register (UPIC) In the UPI mode
port A on the HPC46164 is the data bus UPI can only be
used if the HPC46164 is in the Single-Chip mode
FIGURE 28 HPC46164 as a Peripheral (UPI Interface to Series 32000 Application)
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