DS99R103 Datasheet, PDF (5/22 Pages) National Semiconductor (TI) – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Symbol
t_ROS
t_ROH
t_HZR
t_LZR
t_ZHR
t_ZLR
t_DD
Parameter
ROUT (23:16) Setup Data to
RCLK (Group 3)
ROUT (23:16) Hold Data to
RCLK (Group 3)
HIGH to TRI-STATE Delay
LOW to TRI-STATE Delay
TRI-STATE to HIGH Delay
TRI-STATE to LOW Delay
Deserializer Delay
Conditions
(Figure 15)
(Figure 13)
(Figure 12)
Pin/Freq.
ROUT [23:16]
ROUT [23:0],
RCLK, LOCK
RCLK
t_DRDL
Deserializer PLL Lock Time
from Powerdown
(Figure 14) (Notes 6, 3 MHz
7)
40 MHz
RxIN_TOL_L Receiver INput TOLerance Left (Figure 16)(Notes 5, 3 MHz–40 MHz
9)
RxIN_TOL_R Receiver INput TOLerance
Right
(Figure 16)
(Notes 5, 9)
3 MHz–40 MHz
Min
Typ
Max Units
(0.40)*
t_RCP
(27/56)*t_RCP
ns
(0.40)*
t_RCP
(29/56)*t_RCP
ns
3
10
ns
3
10
ns
3
10
ns
3
10
ns
[4+(3/56)]T [4+(3/56)]T ns
+5.9
+18.5
5
50
ms
5
50
ms
0.25
UI
0.25
UI
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V_DD = 3.3V and T_A = +25°C.
Note 3: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 4: When the Serializer output is at TRI-STATE, the Deserializer will lose PLL lock. Resynchronization MUST occur before data transfer.
Note 5: RxIN_TOL is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a
measurement in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 6: The Deserializer PLL lock time (t_DRDL) may vary depending on input data patterns and the number of transitions within the pattern.
Note 7: Guaranteed by Characterization (GBC) using statistical analysis.
Note 8: t_JIT (@BER of 10e-9) specifies the allowable jitter on TCLK. t_JIT not included in TxOUT_E_O parameter.
Note 9: UI – Unit Interval, equivalent to one ideal serialized data bit width. The UI scales with frequency.
Note 10: Figure 1 Figure 2 Figure 8 Figure 12 Figure 14 show a falling edge data strobe (TCLK IN/RCLK OUT).
Note 11: Figure 5 Figure 15show a rising edge data strobe (TCLK IN/RCLK OUT).
Note 12: TxOUT_E_O is affected by pre-emphasis value.
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