DS99R103 Datasheet, PDF (1/22 Pages) National Semiconductor (TI) – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

April 2007
DS99R103/DS99R104
3-40MHz DC-Balanced 24-Bit LVDS Serializer and
Deserializer
General Description
The DS99R103/104 Chipset translates a 24-bit parallel bus
into a fully transparent data/control LVDS serial stream with
embedded clock information. This single serial stream sim-
plifies transferring a 24-bit bus over PCB traces and cable by
eliminating the skew problems between parallel data and
clock paths. It saves system cost by narrowing data paths that
in turn reduce PCB layers, cable width, and connector size
and pins.
The DS99R103/104 incorporates LVDS signaling on the high-
speed I/O. LVDS provides a low power and low noise envi-
ronment for reliably transferring data over a serial transmis-
sion path. By optimizing the serializer output edge rate for the
operating frequency range EMI is further reduced.
In addition the device features pre-emphasis to boost signals
over longer distances using lossy cables. Internal DC bal-
anced encoding/decoding is used to support AC-Coupled
interconnects.
Features
■ ^{3 MHz–40 MHz clock embedded and DC-Balancing 24:1}
and 1:24 data transmissions
■ ^{Capable to drive shielded twisted-pair cable}
■ ^{User selectable clock edge for parallel data on both}
Transmitter and Receiver
■ ^{Internal DC Balancing encode/decode – Supports AC-}
coupling interface with no external coding required
■ ^{Individual power-down controls for both Transmitter and}
Receiver
■ ^{Embedded clock CDR (clock and data recovery) on}
Receiver and no external source of reference clock
needed
■ ^{All codes RDL (random data lock) to support hot-pluggable}
applications
■ ^{LOCK output flag to ensure data integrity at Receiver side}
■ ^{Balanced T}_SETUP^/T_HOLD ^{between RCLK and RDATA on}
Receiver side
■ ^{PTO (progressive turn-on) LVCMOS outputs to reduce}
EMI and minimize SSO effects
■ ^{All LVCMOS inputs and control pins have internal}
pulldown
■ ^{On-chip filters for PLLs on Transmitter and Receiver}
■ ^{Integrated 100Ω (±20%) termination in Receiver input}
■ ^{4 mA Receiver output drive}
■ ^{48-pin TQFP and 48-pin LLP packages}
■ ^{Pure CMOS .35 μm process}
■ ^{Power supply range 3.3V ± 10%}
■ ^{Temperature range −40°C to +85°C}
■ ^{8 kV HBM ESD structure}
Block Diagram
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