DS99R103 Datasheet, PDF (13/22 Pages) National Semiconductor (TI) – 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

Pin Diagrams
Serializer - DS99R103
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20208019
DS99R104 Deserializer Pin Descriptions
Pin # Pin Name
I/O
Description
LVCMOS PARALLEL INTERFACE PINS
25-28, ROUT[7:0]
31-34
CMOS_O
Receiver Parallel Interface Data Outputs – Group 1
13-16, ROUT[15:8] CMOS_O
21-24
Receiver Parallel Interface Data Outputs – Group 2
3-6, ROUT[23:16] CMOS_O
9-12
Receiver Parallel Interface Data Outputs – Group 3
18 RCLK
CMOS_O Parallel Interface Clock Output Pin. Strobe edge set by RRFB configuration pin.
CONTROL AND CONFIGURATION PINS
43 RRFB
CMOS_I
Receiver Clock Edge Select Pin
RRFB = H; ROUT LVCMOS Outputs strobed on the Rising Clock Edge.
RRFB = L; ROUT LVCMOS Outputs strobed on the Falling Clock Edge.
48 REN
CMOS_I
Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
1
RPWDNB CMOS_I
Receiver Data Enable
REN = H; ROUT[23-0] and RCLK are Enabled (ON).
REN = L; ROUT[23-0] and RCLK are Disabled (OFF), Receiver ROUT[23-0] and RCLK Outputs
are in TRI-STATE, PLL still operational and locked to TCLK.
13
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