DS92LV18_06 Datasheet, PDF (5/20 Pages) National Semiconductor (TI) – 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz

Deserializer Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
HIGH to TRI-STATE
t_HZR
Delay
2.2
LOW to TRI-STATE
t_LZR
Delay
2.2
ROUT(0-17),
Figure 13
TRI-STATE to HIGH
LOCK
t_ZHR
Delay
2.3
TRI-STATE to LOW
t_ZLR
Delay
2.9
t_DD
t_DSR1
Deserializer Delay
Deserializer PLL
Lock Time from
Powerdown (with
SYNCPAT)
Figure 14,
(Note 7) (Note 8)
RCLK
15MHz
66 MHz
1.75*t_RCP + 2.1 1.75*t_RCP + 4.0
3.7
1.9
Deserializer PLL
Figure 15,
15MHz
1.5
t_DSR2
Lock time from
SYNCPAT
(Note 7) (Note 8)
66 MHz
0.9
Ideal Deserializer
Figure 17
t_{RNMI-R Noise Margin Right (Note 6) (Note 8)}
15 MHz
66 MHz
Ideal Deserializer
t_{RNMI-L Noise Margin Left}
Figure 17
(Note 6) (Note 8)
15 MHz
66 MHz
Total Interconnect
t_JI
Jitter Budget
(Note 9)
15 MHz
66 MHz
Max
10
10
10
10
1.75*t_RCP + 6.1
10
4
5
2
1490
180
1460
330
1060
160
Units
ns
ns
ns
ns
ns
µs
µs
µs
µs
ps
ps
ps
ps
ps
ps
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V_CC = 3.3V and T_A = +25˚C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,
VTH and VTL which are differential voltages.
Note 4: Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 5: t_DSR1 is the time required by the deserializer to obtain lock when exiting powerdown mode. t_DSR1 is specified with synchronization patterns (SYNCPATs)
present at the LVDS inputs (RI+ and RI-) before exiting powerdown mode. t_DSR2 is the time required to obtain lock for the powered-up and enabled deserializer when
the LVDS input (RI+ and RI-) conditions change from not receiving data to receiving synchronization patterns. Both t_DSR1 and t_DSR2 are specified with the REFCLK
running and stable.
Note 6: t_RNMI is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a measurement
in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 7: A sync pattern is a fixed pattern with 9-bits of data high followed by 9-bits of data low. The SYNC pattern is automatically generated by the transmitter when
the SYNC pin is pulled high.
Note 8: Guaranteed by Design (GBD) using statistical analysis.
Note 9: Total Interconnect Jitter Budget (t_JI) specifies the allowable jitter added by the interconnect assuming both transmitter and receiver are DS92LV18 circuits.
t_JI is GBD using statistical analysis.
Note 10: The VOD specification is a measurement of the difference between the single-ended VOH and VOL output voltages across a100 ohm load. Applying the
formula OUT+ - OUT- to the differential outputs will result in a waveform with peak to peak amplitude equal to twice the datasheet indicated VOD.
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