DS92LV18_06 Datasheet, PDF (16/20 Pages) National Semiconductor (TI) – 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz

Application Information (Continued)
PVDD = PLL SECTION POWER SUPPLY
The PVDD pin supplies the PLL circuit. Note that the
DS92LV18 has two separate PLL and supply pins. The
PLL(s) require clean power for the minimization of Jitter. A
supply noise frequency in the 300 kHz to 1 MHz range can
cause increased output jitter. Certain power supplies may
have switching frequencies or high harmonic content in this
range. If this is the case, filtering of this noise spectrum may
be required. A notch filter response is best to provide a stable
VDD, suppression of the noise band, and good high-
frequency response (clock fundamental). This may be ac-
complished with a pie filter (CRC or CLC). If employed, a
separate pie filter is recommended for each PLL to minimize
drop in potential due to the series resistance. The pie filter
should be located close to the PVDD power pin. Separate
power planes for the PVDD pins is typically not required.
capacitor is sufficient for these pins. If space is available, a
0.01uF capacitor may be used in parallel with the 0.1uF
capacitor for additional high frequency filtering.
GROUNDS
The AGND pin should be connected to the signal common in
the cable for the return path of any common-mode current.
Most of the LVDS current will be odd-mode and return within
the interconnect pair. A small amount of current may be
even-mode due to coupled noise and driver imbalances.
This current should return via a low impedance known path.
A solid ground plane is recommended for both DVDD, PVDD
or AVDD. Using a split plane may cause ground loops or a
difference in ground potential at various ground pins of the
device.
AVDD = LVDS SECTION POWER SUPPLY
The AVDD pins power the LVDS portion of the circuit. The
DS92LV18 has four AVDD pins. Due to the nature of the
design, current draw is not excessive on these pins. A 0.1uF
Truth Tables
TPWDN (Pin 42)
L
H
H
H
DEN (Pin 19)
X
L
H
H
Transmitter Truth Table
TX PLL Status (Internal)
X
X
Not Locked
Locked
LVDS Outputs (Pins 13 and 14)
Hi Z
Hi Z
Hi Z
Serialized Data with Embedded Clock
RPWDN (Pin 01)
L
H
H
H
REN (Pin 02)
X
L
H
H
Receiver Truth Table
RX PLL Status (Internal) ROUTn & RCLK (See Pin Diagram)
X
Hi Z
X
Hi Z
Not Locked
Locked
H
Data & CLK Active
LOCK (Pin 63)
Hi Z
L = PLL Locked;
H = PLL Unlocked
H
L
www.national.com
16