DS92LV18_06 Datasheet, PDF (11/20 Pages) National Semiconductor (TI) – 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz

AC Timing Diagrams and Test Circuits (Continued)
FIGURE 16. Deterministic Jitter and Ideal Bit Position
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t_RNMI-L is the noise margin on the left of the figure above.
t_RNMI-R is the noise margin on the right of the above figure.
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FIGURE 17. Deserializer Noise Margin (t_RNMI) and Sampling window
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