DS92LV040A Datasheet, PDF (5/12 Pages) National Semiconductor (TI) – 4 Channel Bus LVDS Transceiver

Applications Information (Continued)
existing RS-422 drivers. The TRI-STATE function allows the
driver outputs to be disabled, thus obtaining an even lower
power state when the transmission of data is not required.
There are a few common practices which should be implied
when designing PCB for Bus LVDS signaling. Recom-
mended practices are:
• Use at least 4 PCB board layer (Bus LVDS signals,
ground, power and TTL signals).
• Keep drivers and receivers as close to the (Bus LVDS
port side) connector as possible.
• Bypass each Bus LVDS device and also use distributed
bulk capacitance between power planes. Surface mount
capacitors placed close to power and ground pins work
best. Three or more high frequency, multi-layer ceramic
(MLC) surface mount (0.1 µF, 0.01 µF, 0.001 µF) in
parallel should be used between each V_CC and ground.
Multiple vias should be used to connect V_CC and Ground
planes to the pads of the by-pass capacitors.
In addition, it may be necessary to randomly distribute
by-pass capacitors of different values (200pF to 1000pF)
to achieve different resonant frequencies.
• Use the termination resistor which best matches the dif-
ferential impedance of your transmission line.
• Leave unused Bus LVDS receiver inputs open (floating).
Limit traces on unused inputs to <0.5 inches.
• Isolate TTL signals from Bus LVDS signals
MEDIA (CONNECTOR or BACKPLANE) SELECTION:
• The backplane and connectors should have a matched
differential impedance. Use controlled impedance traces
which match the differential impedance of your transmis-
sion medium (ie. backplane or cable) and termination
resistor(s). Run the differential pair trace lines as close
together as possible as soon as they leave the IC . This
will help eliminate reflections and ensure noise is coupled
as common-mode. In fact, we have seen that differential
signals which are 1mm apart radiate far less noise than
traces 3mm apart since magnetic field cancellation is
much better with the closer traces. Plus, noise induced
on the differential lines is much more likely to appear as
common-mode which is rejected by the receiver. Match
electrical lengths between traces to reduce skew. Skew
between the signals of a pair means a phase difference
between signals which destroys the magnetic field can-
cellation benefits of differential signals and EMI will re-
sult. (Note the velocity of propagation, v = c/Er where c
(the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do
not rely solely on the autoroute function for differential
traces. Carefully review dimensions to match differential
impedance and provide isolation for the differential lines.
Minimize the number of vias and other discontinuity on
the line. Avoid 90˚ turns (these cause impedance discon-
tinuity). Use arcs or 45˚ bevels. Within a pair of traces,
the distance between the two traces should be minimized
to maintain common-mode rejection of the receivers. On
the printed circuit board, this distance should remain
constant to avoid discontinuity in differential impedance.
Minor violations at connection points are allowable.
• Stub Length: Stub lengths should be kept to a minimum.
The typical transition time of the DS92LV040A BLVDS
output is 0.75ns (20% to 80%). The extrapolated 100
percent time is 0.75/0.6 or 1.25ns. For a general approxi-
mation, if the electrical length of a trace is greater than
1/5 of the transition edge, then the trace is considered a
transmission line. For example, 1.25ns/5 is 250 picosec-
onds. Let velocity equal 160ps per inch for a typical
loaded backplane. Then maximum stub length is 250ps/
160ps/in or 1.56 inches. To determine the maximum stub
for your backplane, you need to know the propagation
velocity for the actual conditions (refer to application
notes AN 905 and AN 808).
PACKAGE and SOLDERING INFORMATION:
• Refer to packaging application note AN-1187. This appli-
cation note details the package attachment methods to
achieve the correct solderability and thermal results.
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