DS92LV040A Datasheet, PDF (4/12 Pages) National Semiconductor (TI) – 4 Channel Bus LVDS Transceiver

AC Electrical Characteristics (Continued)
Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 7)
Symbol
Parameter
Conditions
Min
Typ
DIFFERENTIAL RECEIVER TIMING REQUIREMENTS
t_PHLDR
t_PLHDR
t_SDK1R
Differential Prop. Delay High to Low (Note 9)
Differential Prop Delay Low to High (Note 9)
Differential Skew |t_PHLD–t_PLHD| (duty cycle)(Note 10),
(Note 9)
Figures 6, 7,
C_L = 15 pF
1.6
2.4
1.6
2.4
85
t_CCSKR
t_TLHR
t_THLR
t_PHZ
t_PLZ
t_PZH
t_PZL
f_MAXR
Channel to Channel Skew (all 4 channels)(Note 9)
Transition Time Low to High (10% to 90%) (Note 9)
Transition Time High to Low (90% to 10%) (Note 9)
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Guaranteed operation per data sheet up to the Min.
Duty Cycle 45/55%,Transition time ≤ 25% of period
(Note 9)
R_L = 500Ω,
Figures 8, 9,
C_L = 15 pF
0.850
0.850
140
1.250
1.030
3.0
3.0
3.0
3.0
85
125
Max Units
3.2
ns
3.2
ns
160 ps
300 ps
2.0
ns
2.0
ns
10
ns
10
ns
10
ns
10
ns
MHz
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device operation.
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified except
V_OD, ∆V_OD and V_ID.
Note 3: Package must be mounted to pc board in accordance with AN-1187 to achieve thermals.
Note 4: All typicals are given for V_CC = +3.3V and T_A = +25˚C, unless otherwise stated.
Note 5: ESD Rating: HBM (1.5 kΩ, 100 pF) > 4 kV EIAJ (0Ω, 200 pF) > 250.
Note 6: C_L includes probe and fixture capacitance.
Note 7: Generator waveforms for all tests unless otherwise specified: f = 25 MHz, Z_O = 50Ω, t_r, t_f = <1.0 ns (0%–100%). To ensure fastest propagation delay and
minimum skew, data input edge rates should be equal to or faster than 1ns/V; control signals equal to or faster than 3ns/V. In general, the faster the input edge rate,
the better the AC performance.
Note 8: The DS92LV040A functions within datasheet specification when a resistive load is applied to the driver outputs.
Note 9: Propagation delays, transition times, and receiver threshold are guaranteed by design and characterization.
Note 10: t_SKD1 |t_PHLD–t_PLHD| is the worst case pulse skew (measure of duty cycle) over recommended operation conditions.
Note 11: Only one output at a time should be shorted, do not exceed maximum package power dissipation capacity.
Note 12: V_OH fail-safe terminated test performed with 27Ω connected between RI+ and RI− inputs. No external voltage is applied.
Note 13: Chip to Chip skew is the difference in differential propagation delay between any channels of any devices, either edge.
Applications Information
General application guidelines and hints may be found in the
following application notes: AN-808, AN-977, AN-971, and
AN-903.
BLVDS drivers and receivers are intended to be used in a
differential backplane configuration. Transceivers or receiv-
ers are connected to the driver through a balanced media
such as differential PCB traces. Typically, the characteristic
differential impedance of the media (Zo) is in the range of
50Ω to 100Ω. Two termination resistors of ZoΩ each are
placed at the ends of the transmission line backplane. The
termination resistor converts the current sourced by the
driver into a voltage that is detected by the receiver. The
effects of mid-stream connector(s), cable stub(s), and other
impedance discontinuity as well as ground shifting, noise
margin limits, and total termination loading must be taken
into account. The DS92LV040A differential line driver is a
balanced current mode design. A current mode driver, gen-
erally speaking has a high output impedance (100 ohms)
and supplies a reasonably constant current for a range of
loads (a voltage mode driver on the other hand supplies a
constant voltage for a range of loads). Current is switched
through the load in one direction to produce a logic state and
in the other direction to produce the other logic state. The
output current is typically 12 mA. The current changes as a
function of load resistor. The current mode requires (as
discussed above) that a resistive termination be employed to
terminate the signal and to complete the loop. Unterminated
configurations are not allowed. The 12 mA loop current will
develop a differential voltage of about 300mV across a 27Ω
(double terminated 54Ω differential transmission backplane)
effective resistance, which the receiver detects with a 230
mV minimum differential noise margin neglecting resistive
line losses (driven signal minus receiver threshold (300 mV
– 70 mV = 230 mV)). The signal is centered around +1.2V
(Driver Offset, VOS ) with respect to ground. Note that the
steady-state voltage (VSS ) peak-to-peak swing is twice the
differential voltage (VOD ) and is typically 600 mV. The
current mode driver provides substantial benefits over volt-
age mode drivers, such as an RS-422 driver. Its quiescent
current remains relatively flat versus switching frequency.
Whereas the RS-422 voltage mode driver increases expo-
nentially in most case between 20 MHz–50 MHz. This is due
to the overlap current that flows between the rails of the
device when the internal gates switch. Whereas the current
mode driver switches a fixed current between its output
without any substantial overlap current. This is similar to
some ECL and PECL devices, but without the heavy static
ICC requirements of the ECL/PECL designs. LVDS requires
80% less current than similar PECL devices. AC specifica-
tions for the driver are a tenfold improvement over other
www.national.com
4