DS92LV040A Datasheet, PDF (11/12 Pages) National Semiconductor (TI) – 4 Channel Bus LVDS Transceiver

Pinout Description
Pin Name
DO+/RI+
DO−/RI−
D_IN
RO
RE12
Pin #
14, 16, 19, 21
13, 15, 18, 20
35, 37, 40, 42
36, 38, 41, 43
29
RE34
5
DE12
26
DE34
8
GND
V_CC
AGND
AV_CC
NC
DAP
4, 28, 31, 39
3, 6, 30
9, 17, 25
7, 10, 22, 27
1, 2, 11, 12, 23, 24,
32, 33, 34, 44
Input/Output
I/O
I/O
I
O
I
I
I
I
Ground
Power
Ground
Power
N/A
Descriptions
True Bus LVDS Driver Outputs and Receiver Inputs.
Complimentary Bus LVDS Driver Outputs and Receiver Inputs.
LVTTL Driver Input. No pull up or pull down is attached to this pin
LVTTL Receiver Output.
Receiver Enable LVTTL Input (Active Low). This pin, when low,
configures receiver outputs, RO1 and RO2 active. When this pin is
high, RO1 and RO2 are TRI-STATE. If this pin is floating, a weak
current source to V_CC causes RO1 and RO2 to be TRI-STATE
Receiver Enable LVTTL Input (Active Low). This pin, when low,
configures receiver outputs, RO3 and RO4 active. When this pin is
high, RO3 and RO4 are TRI-STATE. If this pin is floating, a weak
current source to V_CC causes RO3 and RO4 to be TRI-STATE
Driver Enable LVTTL Input (Active High). This pin, when high,
configures driver outputs, DO1+/RIN1+, DO1−/RIN1− and
DO2+/RIN2+, DO2−/RIN2− active. When this pin is low, driver outputs
1 and 2 are TRI-STATE. If this pin is floating, a weak current source
to V_CC causes driver outputs 1 and 2 to be active
Driver Enable LVTTL Input (Active High). This pin, when high,
configures driver outputs, DO3+/RIN3+, DO3−/RIN3− and
DO4+/RIN4+, DO4−/RIN4− active. When this pin is low, driver outputs
3 and 4 are TRI-STATE. If this pin is floating, a weak current source
to V_CC causes driver outputs 3 and 4 to be active
Ground for digital circuitry (must connect to GND on PC board). These
pins connected internally.
V_CC for digital circuitry (must connect to V_CC on PC board). These
pins connected internally.
Ground for analog circuitry (must connect to GND on PC board).
These pins connected internally.
Analog V_CC (must connect to V_CC on PC board). These pins
connected internally.
Reserved for future use, leave open circuit.
GND
Must connect to GND plane through vias to achieve the theta ja
specified under Absolute Maximum Ratings. The DAP (die attach pad)
is the heat transfer material that is centered on the bottom of the LLP
package. Refer to application note AN-1187 for attachment details.
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