DS90LV012A Datasheet, PDF (5/8 Pages) National Semiconductor (TI) – 3V LVDS Single CMOS Differential Line Receiver

Applications Information (Continued)
Power Decoupling Recommendations:
Bypass capacitors must be used on power pins. Use high
frequency ceramic (surface mount is recommended) 0.1µF
and 0.001µF capacitors in parallel at the power supply pin
with the smallest value capacitor closest to the device supply
pin. Additional scattered capacitors over the printed circuit
board will improve decoupling. Multiple vias should be used
to connect the decoupling capacitors to the power planes. A
10µF (35V) or greater solid tantalum capacitor should be
connected at the power entry point on the printed circuit
board between the supply and ground.
PC Board considerations:
Use at least 4 PCB board layers (top to bottom): LVDS
signals, ground, power, TTL signals.
Isolate TTL signals from LVDS signals, otherwise the TTL
signals may couple onto the LVDS lines. It is best to put TTL
and LVDS signals on different layers which are isolated by a
power/ground plane(s).
Keep drivers and receivers as close to the (LVDS port side)
connectors as possible.
For PC board considerations for the LLP package, please
refer to application note AN-1187 “Leadless Leadframe
Package.” It is important to note that to optimize signal
integrity (minimize jitter and noise coupling), the LLP thermal
land pad, which is a metal (normally copper) rectangular
region located under the package, should be attached to
ground and match the dimensions of the exposed pad on the
PCB (1:1 ratio).
Differential Traces:
Use controlled impedance traces which match the differen-
tial impedance of your transmission medium (ie. cable) and
termination resistor. Run the differential pair trace lines as
close together as possible as soon as they leave the IC
(stubs should be < 10mm long). This will help eliminate
reflections and ensure noise is coupled as common-mode.
In fact, we have seen that differential signals which are 1mm
apart radiate far less noise than traces 3mm apart since
magnetic field cancellation is much better with the closer
traces. In addition, noise induced on the differential lines is
much more likely to appear as common-mode which is re-
jected by the receiver.
Match electrical lengths between traces to reduce skew.
Skew between the signals of a pair means a phase differ-
ence between signals which destroys the magnetic field
cancellation benefits of differential signals and EMI will re-
sult! (Note that the velocity of propagation, v = c/E _r where c
(the speed of light) = 0.2997mm/ps or 0.0118 in/ps). Do not
rely solely on the autoroute function for differential traces.
Carefully review dimensions to match differential impedance
and provide isolation for the differential lines. Minimize the
number of vias and other discontinuities on the line.
Avoid 90˚ turns (these cause impedance discontinuities).
Use arcs or 45˚ bevels.
Within a pair of traces, the distance between the two traces
should be minimized to maintain common-mode rejection of
the receivers. On the printed circuit board, this distance
should remain constant to avoid discontinuities in differential
impedance. Minor violations at connection points are allow-
able.
Termination:
DS90LV012A:
Use a termination resistor which best matches the differen-
tial impedance or your transmission line. The resistor should
be between 90Ω and 130Ω. Remember that the current
mode outputs need the termination resistor to generate the
differential voltage. LVDS will not work without resistor ter-
mination. Typically, connecting a single resistor across the
pair at the receiver end will suffice.
Surface mount 1% - 2% resistors are the best. PCB stubs,
component lead, and the distance from the termination to the
receiver inputs should be minimized. The distance between
the termination resistor and the receiver should be < 10mm
(12mm MAX).
DS90LT012A:
The DS90LT012A integrates the terminating resistor for
point-to-point applications. The resistor value will be be-
tween 90Ω and 133Ω.
Threshold:
The LVDS Standard (ANSI/TIA/EIA-644-A) specifies a maxi-
mum threshold of ±100mV for the LVDS receiver. The
DS90LV012A and DS90LT012A support an enhanced
threshold region of −100mV to 0V. This is useful for fail-safe
biasing. The threshold region is shown in the Voltage Trans-
fer Curve (VTC) in Figure 5. The typical DS90LV012A or
DS90LT012A LVDS receiver switches at about −30mV. Note
that with V_ID = 0V, the output will be in a HIGH state. With an
external fail-safe bias of +25mV applied, the typical differen-
tial noise margin is now the difference from the switch point
to the bias point. In the example below, this would be 55mV
of Differential Noise Margin (+25mV − (−30mV)). With the
enhanced threshold region of −100mV to 0V, this small
external fail-safe biasing of +25mV (with respect to 0V) gives
a DNM of a comfortable 55mV. With the standard threshold
region of ±100mV, the external fail-safe biasing would need
to be +25mV with respect to +100mV or +125mV, giving a
DNM of 155mV which is stronger fail-safe biasing than is
necessary for the DS90LV012A or DS90LT012A. If more
DNM is required, then a stronger fail-safe bias point can be
set by changing resistor values.
20015029
FIGURE 5. VTC of the DS90LV012A and DS90LT012A LVDS Receivers
5
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