DS90LV012A Datasheet, PDF (4/8 Pages) National Semiconductor (TI) – 3V LVDS Single CMOS Differential Line Receiver

Parameter Measurement Information (Continued)
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FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms
Typical Application
Balanced System
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FIGURE 3. Point-to-Point Application (DS90LV012A)
Balanced System
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FIGURE 4. Point-to-Point Application (DS90LT012A)
Applications Information
General application guidelines and hints for LVDS drivers
and receivers may be found in the following application
notes: LVDS Owner’s Manual (lit #550062-002), AN-808,
AN-977, AN-971, AN-916, AN-805, AN-903.
LVDS drivers and receivers are intended to be primarily used
in an uncomplicated point-to-point configuration as is shown
in Figure 3. This configuration provides a clean signaling
environment for the fast edge rates of the drivers. The re-
ceiver is connected to the driver through a balanced media
which may be a standard twisted pair cable, a parallel pair
cable, or simply PCB traces. Typically the characteristic
impedance of the media is in the range of 100Ω. A termina-
tion resistor of 100Ω should be selected to match the media,
and is located as close to the receiver input pins as possible.
The termination resistor converts the driver output (current
mode) into a voltage that is detected by the receiver. Other
configurations are possible such as a multi-receiver configu-
ration, but the effects of a mid-stream connector(s), cable
stub(s), and other impedance discontinuities as well as
ground shifting, noise margin limits, and total termination
loading must be taken into account.
The DS90LV012A and DS90LT012A differential line receiv-
ers are capable of detecting signals as low as 100 mV, over
a ±1V common-mode range centered around +1.2V. This is
related to the driver offset voltage which is typically +1.2V.
The driven signal is centered around this voltage and may
shift ±1V around this center point. The ±1V shifting may be
the result of a ground potential difference between the driv-
er’s ground reference and the receiver’s ground reference,
the common-mode effects of coupled noise, or a combina-
tion of the two. The AC parameters of both receiver input
pins are optimized for a recommended operating input volt-
age range of 0V to +2.4V (measured from each pin to
ground). The device will operate for receiver input voltages
up to V_DD, but exceeding V_DD will turn on the ESD protection
circuitry which will clamp the bus voltages.
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