DS08MB200 Datasheet, PDF (5/8 Pages) National Semiconductor (TI) – Dual 800 Mbps 1:2/2:1 LVDS Mux/Buffer

Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
SUPPLY CURRENT (Static)
I_CC
Supply Current
All inputs and outputs enabled and
active, terminated with differential load
of 100Ω between OUT+ and OUT-.
I_CCZ
Supply Current - Powerdown
ENA_0 = ENB_0 = ENL_0= ENA_1 =
Mode
ENB_1 = ENL_1 = L
SWITCHING CHARACTERISTICS — LVDS OUTPUTS
t_LHT
Differential Low to High Transition Use an alternating 1 and 0 pattern at
Time
200 Mb/s, measure between 20% and
t_HLT
Differential High to Low Transition ^{80% of V}OD^{. (Note 15)}
Time
t_PLHD
t_PHLD
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Use an alternating 1 and 0 pattern at
200 Mb/s, measure at 50% V_OD
between input to output.
t_SKD1
t_SKCC
Pulse Skew
Output Channel to Channel Skew
|t_PLHD–t_PHLD| (Note 15)
Difference in propagation delay (t_PLHD
or t_PHLD) among all output channels.
(Note 15)
t_JIT
Jitter
(Note 11)
RJ - Alternating 1 and 0 at 400 MHz
(Note 12)
DJ - K28.5 Pattern, 800 Mbps (Note 13)
TJ - PRBS 2⁷-1 Pattern, 800 Mbps
(Note 14)
t_ON
LVDS Output Enable Time
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from TRI-STATE to
active.
t_ON2
LVDS Output Enable time from Time from ENA_n, ENB_n, or ENL_n to
powerdown mode
OUT± change from Powerdown to
active
t_OFF
LVDS Output Disable Time
Time from ENA_n, ENB_n, or ENL_n to
OUT± change from active to
TRI-STATE or powerdown.
Typ
(Note 8)
225
0.6
170
170
1.0
1.0
25
50
1.3
15
16
0.5
10
Max
275
4.0
250
250
2.5
2.5
75
115
1.5
34
34
1.5
20
12
Units
mA
mA
ps
ps
ns
ns
ps
ps
psrms
psp-p
psp-p
µs
µs
ns
Note 8: Typical parameters are measured at V_DD = 3.3V, T_A = 25˚C. They are for reference purposes, and are not production-tested.
Note 9: Differential output voltage V_OD is defined as ABS(OUT+–OUT−). Differential input voltage V_ID is defined as ABS(IN+–IN−).
Note 10: Output offset voltage V_OS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states.
Note 11: Jitter is not production tested, but guaranteed through characterization on a sample basis.
Note 12: Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = V_ID = 500mV, 50% duty cycle at 400
MHz, t_r = t_f = 50ps (20% to 80%).
Note 13: Deterministic Jitter, or D_J, is measured to a histogram mean with a sample size of 350 hits. Stimulus and fixture jitter has been subtracted. The input
voltage = V_ID = 500mV, K28.5 pattern at 800 Mbps, t_r = t_f = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101).
Note 14: Total Jitter, or T_J, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture jitter has been subtracted. The input voltage
= V_ID = 500mV, 2^7-1 PRBS pattern at 800 Mbps, t_r = t_f = 50ps (20% to 80%).
Note 15: Not production tested. Guaranteed by statistical analysis on a sample basis at the time of characterization.
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